CS4272-CZZ Cirrus Logic Inc, CS4272-CZZ Datasheet - Page 44

• Manufacturer Part Number: CS4272-CZZ
• Description: IC CODEC AUD 24BIT 114DB 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4272-CZZ

• Package / Case: 28-TSSOP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1004 - EVAL BOARD CS4272 STEREO CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1042-5

8.7.3
8.7.4
8.7.5
8.8
8.8.1
8.8.2
44
PART3
B7
Chip ID - Register 08h
Function:
Function:
Function:
This is a Read-Only register.
Function:
Function:
Freeze (Bit 2)
Control Port Enable (Bit 1)
Power Down (Bit 0)
Chip ID (Bits 7:4)
Chip Revision (Bits 3:0)
This function allows modifications to the control port registers without the changes taking effect until
FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneous-
ly, set the FREEZE bit, make all register changes, then clear the FREEZE bit.
This bit is cleared by default, allowing the device to power-up in Stand-Alone Mode. Control Port
Mode can be accessed by setting this bit. This will allow the operation of the device to be controlled
by the registers and the pin definitions will conform to Control Port Mode. See “Recommended Power-
Up Sequence - Access to Control Port Mode” on page 27.
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default
and must be cleared before normal operation in Control Port Mode can occur. The contents of the
control registers are retained when the device is in power-down.
Chip ID code for the CS4272. Permanently set to 0000b (0h).
Chip Revision code for the CS4272.
Revision A is coded as 0000b (0h).
Revision B is coded as 0000b (0h).
PART2
B6
PART1
B5
PART0
B4
REV3
B3
REV2
B2
REV1
B1
CS4272
REV0
DS593F1
B0