CS42526-CQZ Cirrus Logic Inc, CS42526-CQZ Datasheet - Page 78

• Manufacturer Part Number: CS42526-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42526-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPS
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/6 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1037

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10.APPENDIX C: PLL FILTER
The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update information to
the PLL. This results in the PLL being immune to data-dependent jitter effects because the S/PDIF preambles do
not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. The
nominal center sample rate is the sample rate that the PLL first locks onto upon application of an S/PDIF data
stream.
10.1 External Filter Components
10.1.1 General
Configuration 1
Configuration 2
Configuration 3
The PLL behavior is affected by the external filter component values and the locking mode as configured
by the LOCKM[1:0] bits in register 24h.
values and their associated locking modes.
INPUT
RFILT (kΩ) CFILT (µF) CRIP (pF) LOCKM[1:0]
2.55
2.55
1.37
and Charge Pump
Table 21. External PLL Component Values & Locking Modes
Comparator
Phase
÷
0.047
0.047
0.022
N
Figure 27. PLL Block Diagram
2200
2200
1000
Table 21
CFILT
RFILT
shows the supported configurations of PLL component
00
01
10
CRIP
Used for backward compatibility with Revision C
increased wideband jitter. Use this configuration
Provides improved in-band jitter rejection, with
Provides improved wideband jitter rejection in
Default configuration for Revision D devices.
for best DAC and ADC performance when
clocked from the PLL recovered clock.
Double- and Quad-Speed modes.
VCO
devices.
Notes
RMCK
CS42526
DS585F1