MAX9860ETG+ Maxim Integrated Products, MAX9860ETG+ Datasheet
MAX9860ETG+
Specifications of MAX9860ETG+
Related parts for MAX9860ETG+
MAX9860ETG+ Summary of contents
Page 1
... Supports Master Clock Frequencies from 10MHz to 60MHz ♦ Supports Sample Rates from 8kHz to 48kHz ♦ Flexible Digital Audio Interface ♦ Clickless/Popless Operation ♦ 2-Wire, I ♦ Available in 24-Pin, Thin QFN, 4mm x 4mm x 0.8mm Package PART MAX9860ETG+ + Denotes a lead-free/RoHS-compliant package Exposed pad. Applications DIGITAL AUDIO INPUT/OUTPUT Features = 48kHz) S ...
Page 2
Mono Audio Voice Codec ABSOLUTE MAXIMUM RATINGS (Voltages referenced to AGND.) DVDDIO, SDA, SCL, IRQ.......................................-0.3V to +3.6V AVDD, DVDD............................................................-0.3V to +2V AGND, DGND, MICGND .......................................-0.3V to +0.3V OUTP, OUTN, PREG, REF, MICBIAS ......-0.3V to (AVDD + 0.3V) MICLP, MICLN, ...
Page 3
ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD DVDD DVDDIO 1µ +20dB, A PREG REG VPRE Typical values are +25°C.) (Note 2) A PARAMETER SYMBOL Power-Supply Rejection ...
Page 4
Mono Audio Voice Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD DVDD DVDDIO 1µ +20dB, A PREG REG VPRE Typical values are +25°C.) (Note 2) ...
Page 5
ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD DVDD DVDDIO 1µ +20dB, A PREG REG VPRE Typical values are +25°C.) (Note 2) A PARAMETER SYMBOL 5th Order ...
Page 6
Mono Audio Voice Codec ELECTRICAL CHARACTERISTICS (continued +1.8V, R AVDD DVDD DVDDIO 1µ +20dB, A PREG REG VPRE Typical values are +25°C.) (Note 2) ...
Page 7
DIGITAL AUDIO INTERFACE ELECTRICAL CHARACTERISTICS ( 1.8V, unless otherwise noted.) (Note 2) DVDD DVDDIO PARAMETER SYMBOL BCLK Cycle Time t BCLK High Time t BCLK Low Time t BCLK or LRCLK Rise and Fall Time SDIN or ...
Page 8
Mono Audio Voice Codec INTERFACE ELECTRICAL CHARACTERISTICS (continued 1.8V, unless otherwise noted.) (Note 2) DVDD DVDDIO PARAMETER SYMBOL SDA Transmitting Fall Time Setup Time for STOP Condition t SU,STO Bus Capacitance Pulse ...
Page 9
+1.8V, R AVDD DVDD DVDDIO 1µ 1µF A PREG REG MICBIAS TOTAL HARMONIC DISTORTION + NOISE vs. OUTPUT POWER (DAC TO HP 32Ω L ...
Page 10
Mono Audio Voice Codec (V = +1.8V +1.8V, R AVDD DVDD DVDDIO 1µ 1µF A PREG REG MICBIAS POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (MIC TO ADC) 0 -10 -20 ...
Page 11
+1.8V, R AVDD DVDD DVDDIO 1µ 1µF A PREG REG MICBIAS 0dBFS FFT (MICL TO ADC) 20 MCLK = 13MHz LRCLK = 8kHz 0 PLL ENABLED -20 ...
Page 12
Mono Audio Voice Codec (V = +1.8V +1.8V, R AVDD DVDD DVDDIO 1µ 1µF A PREG REG MICBIAS HEADPHONE STARTUP WAVEFORM SDA (2V/div) SPK+ -SPK- (1V/div) TIME (4ms/div) SOFT-START ...
Page 13
PIN NAME Microphone Bias. +1.55V microphone bias for internal and/or external microphone. An external resistor from 1 MICBIAS 2.2kΩ to 470Ω should be used to set the microphone current. Bypass to MICGND with a 1µF capacitor. 2 REG Internal Bias. ...
Page 14
Mono Audio Voice Codec Detailed Description The MAX9860 is a low-power, voiceband, mono audio codec designed to provide a complete audio solution for wireless voice headsets and other mono audio devices. The mono playback path accepts digital audio over ...
Page 15
Table Register Map REGISTER B7 B6 STATUS/INTERRUPT Interrupt Status CLD SLD Microphone NG/AGC NG Readback Interrupt Enable ICLD ISLD CLOCK CONTROL System Clock 0 0 Stereo Audio Clock PLL Control High Stereo Audio Clock Control Low ...
Page 16
Mono Audio Voice Codec Status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. The status register bits are cleared upon a read operation of the status register and are set the next ...
Page 17
The MAX9860 can work with a master clock (MCLK) supplied from any system clock within the range of 10MHz to 60MHz. Internally, the MAX9860 requires a 10MHz to 20MHz clock so a prescaler divides ...
Page 18
Mono Audio Voice Codec Table 3. Clock Control Registers (continued) BITS PLL Enable 0 = (Valid for slave and master mode)—The frequency of LRCLK is set by the NHI and NLO divider bits. Set PLL = 0 in slave ...
Page 19
Digital Audio Interface The MAX9860’s digital audio interface supports a wide range of operating modes to ensure maximum compati- bility. See Figures 1 through 4 for timing diagrams. In Table 5. Digital Audio Interface Registers REGISTER ADDRESS B7 0x06 MAS ...
Page 20
Mono Audio Voice Codec Table 5. Digital Audio Interface Registers (continued) BITS ADC Delay Mode 0 = SDOUT data is valid on the first BCLK edge following an LRCLK edge SDOUT data is delayed one BCLK cycle ...
Page 21
AUDIO MASTER MODES (ST = 1): LEFT JUSTIFIED : WCI = 0, _BCI = 0, _DLY = 0 7ns (typ) LEFT LRCLK RELATIVE TO PCLK (NOTE 7) D15 D14 D13 D12 D11 D10 ...
Page 22
Mono Audio Voice Codec VOICE (TDM) MASTER MODES: _BCI = 0, HIZ = 7ns (typ) LRCLK RELATIVE TO PCLK (NOTE 8) SDOUT L15 L14 L13 L12 L11 L10 ...
Page 23
AUDIO SLAVE MODES (ST = 1): LEFT JUSTIFIED: WCI = 0, _BCI = 0, _DLY = 0 LEFT LRCLK 25ns (min) SDOUT D15 D14 D13 D12 D11 D10 40ns (max) ...
Page 24
Mono Audio Voice Codec VOICE (TDM) SLAVE MODES: _BCI = 0, HIZ = LRCLK 25ns (min) SDOUT L15 L14 L13 L12 L11 L10 40ns (max) 0ns ...
Page 25
The MAX9860 incorporates selecable highpass and notch filters for both the playback and record paths. Each filter is valid for a specific sample rate. Table 6. Digital Filter Registers REGISTER ADDRESS B7 0x08 BITS AVFLT ADC Voice Filter Frequency Select. ...
Page 26
Mono Audio Voice Codec Digital Level Control The MAX9860 includes digital gain adjustment for the playback and record paths. Independent gain Table 8. Digital Level Control Registers REGISTER ADDRESS B7 0x09 0x0A 0x0B 0 BITS DAC Level Adjust Adjusts ...
Page 27
Table 8. Digital Level Control Registers (continued) BITS Left and Right ADC Output Level Adjusts the digital audio level output by the ADCs. CODE 0x0 0x1 0x2 0x3 0x4 0x5 ADCRL/ADCLL 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE ...
Page 28
Mono Audio Voice Codec Microphone Inputs The MAX9860 provides two differential microphone inputs and a low-noise 1.55V microphone bias for power- ing the microphones. In typical applications, the left microphone is used to record a voice signal and the ...
Page 29
Table 9. Microphone Input Register REGISTER ADDRESS B7 0x0C 0 BITS Left and Right Microphone Preamp Gain CODE 00 PAM Note: Selecting 00 disables the microphone inputs and microphone bias automatically. Left and Right Microphone PGA CODE ...
Page 30
Mono Audio Voice Codec Automatic Gain Control (AGC) The MAX9860 includes AGC on both microphone inputs. AGC is enabled by setting the hold time through AGCHLD. AGC dynamically controls the analog PGA microphone input gain to hold the level ...
Page 31
Table 10. AGC and Noise Gate Registers (continued) BITS Noise Gate Threshold The signal level at which the noise gate begins reducing the gain. When the signal level is above the threshold the noise gate has no effect. When the ...
Page 32
Mono Audio Voice Codec Power Management The MAX9860 includes complete power management control to minimize power usage. The DAC and both Table 11. Power Management Register REGISTER ADDRESS B7 SHDN 0x10 BITS Active-Low Software Shutdown 0 = MAX9860 is ...
Page 33
SDA t SU,DAT t LOW t SCL HIGH t HD,STA t R START CONDITION Figure 6. 2-Wire Interface Timing Diagram One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period ...
Page 34
Mono Audio Voice Codec SCL SDA Figure 7. START (S), STOP (P), and REPEATED START (Sr) Conditions START CONDITION SCL SDA Figure 8. Acknowledge ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS 0 R/W Figure 9. Writing One Byte of Data ...
Page 35
ACKNOWLEDGE FROM MAX9860 ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS 0 A R/W Figure 10. Writing N Bytes of Data to the MAX9860 ACKNOWLEDGE FROM MAX9860 ACKNOWLEDGE FROM MAX9860 S SLAVE ADDRESS 0 A R/W Figure 11. Reading One Byte of ...
Page 36
Mono Audio Voice Codec Pin Configuration TOP VIEW MICBIAS REG PREG 3 MAX9860 REF 4 AGND 5 *EP AVDD THIN QFN 4mm x 4mm *EP ...
Page 37
SDOUT MONO 16 SDIN DIGITAL AUDIO P INTERFACE P 17 LRCLK 18 BCLK P DVDDIO P P 10kΩ IRQ 19 TIMING AND CONTROL LOGIC MCLK 14 DVDDIO 1.5kΩ 1.5kΩ SCL 10 STATUS SERIAL PORT SDA 9 ...
Page 38
Mono Audio Voice Codec For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 24 TQFN-EP 38 ______________________________________________________________________________________ Package Information PACKAGE CODE T2444+4 DOCUMENT NO. 21-0139 ...
Page 39
For the latest package outline information and land patterns www.maxim-ic.com/packages. ______________________________________________________________________________________ 16-Bit Mono Audio Voice Codec Package Information (continued) 39 ...
Page 40
... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...