DS1822+PAR Maxim Integrated Products, DS1822+PAR Datasheet - Page 17
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DS1822+PAR
Manufacturer Part Number
DS1822+PAR
Description
Board Mount Temperature Sensors 1-Wire Digital Thermometer
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1822Z.pdf
(21 pages)
Specifications of DS1822+PAR
Full Temp Accuracy
+/- 3 C
Package / Case
TO-92
Digital Output - Bus Interface
Serial (1-Wire)
Digital Output - Number Of Bits
12 bit
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 55 C
Output Type
Digital
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
data from the DS1822 is valid for 15μs after the falling edge that initiated the read time slot. Therefore,
the master must release the bus and then sample the bus state within 15μs from the start of the slot.
Figure 15 illustrates that the sum of T
Figure 16 shows that system timing margin is maximized by keeping T
and by locating the master sample time during read time slots towards the end of the 15μs period.
DETAILED MASTER READ 1 TIMING Figure 15
RECOMMENDED MASTER READ 1 TIMING Figure 16
RELATED APPLICATION NOTES
The following Application Notes can be applied to the DS1822. These notes can be obtained from the
Dallas Semiconductor “Application Note Book,” via the Dallas website at http://www.dalsemi.com/, or
through our faxback service at (214) 450–0441.
Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor
Touch Memory Product
Application Note 55: Extending the Contact Range of Touch Memories
Application Note 74: Reading and Writing Touch Memories via Serial Interfaces
Application Note 104: Minimalist Temperature Control Demo
Application Note 106: Complex MicroLANs
Application Note 108: MicroLAN—In the Long Run
Application Note 162: Interfacing the DS18X20/DS1822 1-Wire Temperature Sensor in a
Microcontroller Environment
Sample 1-Wire subroutines that can be used in conjunction with AN74 can be downloaded from the
Dallas website or anonymous FTP Site.
1-WIRE BUS
GND
1-WIRE BUS
GND
V
V
PU
PU
small
T
INT
=
small
T
RC
=
T
INT
> 1μs
VIH of Master
INIT
LINE TYPE LEGEND
, T
RC
Bus master pulling low
Resistor pullup
, and T
17 of 21
15 μs
15μs
T
SAMPLE
RC
must be less than 15μs for a read time slot.
VIH of Master
Master samples
Master samples
INIT
and T
RC
as short as possible
DS1822