CS42418-DQZ Cirrus Logic Inc, CS42418-DQZ Datasheet - Page 46
CS42418-DQZ
Manufacturer Part Number
CS42418-DQZ
Description
IC CODEC 8CH 110DB 192KHZ 64LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet
1.CS42418-CQZ.pdf
(73 pages)
Specifications of CS42418-DQZ
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 110
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
8
No. Of Input Channels
2
No. Of Output Channels
15
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
110dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS42418-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS42418-DQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
46
6.5.4
6.6
6.6.1
6.6.2
6.6.3
Ext ADC SCLK
7
CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)
Misc Control (address 05h)
EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)
RMCK HIGH IMPEDANCE (HIZ_RMCK)
FREEZE CONTROLS (FREEZE)
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
Default = 0
Function:
This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC. By de-
fault, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits.
0 - 24 bit mode.
1 - 16 bit mode.
This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using
One-Line Mode of operation.
0 - ADC_SCLK is used as external ADC SCLK.
1 - DAC_SCLK is used as external ADC SCLK.
This bit is used to create a high-impedance output on RMCK when the clock signal is not required.
This function will freeze the previous output of, and allow modifications to be made to, the Volume
Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
HiZ_RMCK
6
Reserved
5
FREEZE
4
FILT_SEL
3
HPF_FREEZE
2
DAC_SP
M/S
1
CS42418
ADC_SP
DS603F1
M/S
0