CS42526-DQZ Cirrus Logic Inc, CS42526-DQZ Datasheet - Page 54

• Manufacturer Part Number: CS42526-DQZ
• Description: IC CODEC S/PDIF RCVR 64-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42526-DQZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 6
• No. Of Input Channels: 2
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 114dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

54
6.7.4
6.7.5
6.8
6.8.1
6.9
Digital Silence AES Format2 AES Format1 AES Format0
RATIO7(2
7
7
MASTER CLOCK SOURCE SELECT (SW_CTRLX)
FORCE PLL LOCK (FRC_PLL_LK)
OMCK/PLL_CLK Ratio (address 07h) (Read Only)
OMCK/PLL_CLK RATIO (RATIOX)
RVCR Status (address 08h) (Read Only)
Default = 00
Function:
Default = 0
Function:
Default = xxxxxxxx
Function:
1
)
SW_CTRL1 SW_CTRL0 UNLOCK
These two bits, along with the UNLOCK bit in register
on page
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.
When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes
unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.
This bit is used to enable the PLL to lock to the S/PDIF input stream or the SAI_LRCK with the ab-
sence of a clock signal on OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will
be disabled and the SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h)
(Read Only) register contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the
DE-EMPH[1:0] bits to properly apply de-emphasis filtering.
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
RATIO6(2
0
0
1
1
6
6
64, determine the master clock source for the CS42526. When SW_CTRL1 and SW_CTRL0
0
)
RATIO5(2
0
1
0
1
5
5
-1
Table 12. Master Clock Source Select
)
RATIO4(2
X
X
0
1
0
1
4
4
Manual setting, MCLK sourced from PLL.
Manual setting, MCLK sourced from OMCK.
Hold, keep same MCLK source.Auto switch, MCLK
sourced from OMCK.
Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.
-2
)
RATIO3(2
Active_CLK
3
3
-3
“Interrupt Status (address 20h) (Read Only)”
)
Description
RVCR_CLK2
RATIO2(2
2
2
-4
)
RVCR_CLK1
RATIO1(2
1
1
-5
)
CS42526
RVCR_CLK0
RATIO0(2
DS585F1
0
0
-6
)