W681360RG TR Nuvoton Technology Corporation of America, W681360RG TR Datasheet - Page 14

• Manufacturer Part Number: W681360RG TR
• Description: IC VOICEBAND CODEC 3V 1CH 20SSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Type: PCMr

Specifications of W681360RG TR

• Data Interface: PCM Audio Interface
• Resolution (bits): 13 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 2.7 V ~ 5.25 V
• Voltage - Supply, Digital: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• For Use With: W681360ES - KIT EVAL FOR W681360
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: W681360RG T&R; W681360RG T&R

The system can work at 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz &
4800kHz master clock rates. The system clock is supplied through the master clock input MCLK and
can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256kHz
and 8kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If both Frame Syncs are
LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the
W681360 will enter the low power standby mode. Another way to power down is to set the PUI pin to
LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
transmit Frame Sync pulse needs to be present. It will take two transmit Frame Sync cycles before the
pin PCMT becomes low impedance.
The on-chip power amplifier is typically used to drive an external loudspeaker. The inverting input to
the power amplifier is available at pin PAI. The non-inverting input is tied internally to V
inverting output PAO– is used to provide a feedback signal to the PAI pin to set the gain of the power
amplifier outputs (PAO+ and PAO-). These push–pull outputs are capable of driving a 300Ω load to
1.772 V
Connecting PAI to V
will be high impedance.
LONG FRAM E
SHORT O R
FST (FSR)
(BCLKR)
BCLKT
SYNC
7.5. O
PCMR
PCMT
PEAK
7.4.4. System Timing
N
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-C
HIP
P
Transm it and Receive both use BCLKT. FST m ay occur at a different tim e than FSR.
DD
OWER
1
1
Bits 14, 15, and 16, clocked into PCMR, are used for attenuation control for the
will power down the power driver amplifiers and the PAO+ and PAO– outputs
FIGURE 7.7: RECEIVE GAIN ADJUST TIMING MODE
2
2
A
MPLIFIER
3
3
4
4
5
5
Receive Gain Adjust (BCLKR=1)
6
6
receive analog output.
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7
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Publication Release Date: September 2005
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W681360
AG.
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The
Revision A.2
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