SGTL5000XNLA3R2 Freescale Semiconductor, SGTL5000XNLA3R2 Datasheet - Page 45

• Manufacturer Part Number: SGTL5000XNLA3R2
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3R2

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000 EA2 DS-0-3
6.2.
Chip Configuration
6.2.1.
All outputs (LINEOUT, HP_OUT, I2S_OUT) are muted by default on powerup. To
avoid any pops/clicks, the outputs should remain muted during these chip configura-
tion steps. Refer to section 6.2.6 for volume and mute control.
Initialization
6.2.1.1.
After the power supplies for chip is turned on, following initialization sequence
should be followed. Please note that certain steps may be optional or different val-
ues may need to be written based on the power supply voltage used and desired
configuration.
VDDA = 1.8V.
//--------------- Power Supply Configuration----------------
// NOTE:
// internally driven by the chip
// Configure VDDD level to 1.2V (bits 3:0)
Write CHIP_LINREG_CTRL
// Power up internal linear regulator (Set bit 9)
Write CHIP_ANA_POWER
// NOTE:
// externally driven
// Turn off startup power supplies to save power (Clear bit 12 and 13)
Write CHIP_ANA_POWER
// NOTE:
// VDDIO power supplies are less than 3.1V.
// Enable the internal oscillator for the charge pump (Set bit 11)
Write CHIP_CLK_TOP_CTRL
// Enable charge pump (Set bit 11)
Write CHIP_ANA_POWER
// NOTE:
// VDDIO are greater than 3.1V
// Configure the chargepump to use the VDDIO rail (set bit 5 and bit 6)
Write CHIP_LINREG_CTRL
//------ Reference Voltage and Bias Current Configuration----------
// NOTE:
// on the VDDA voltage value.
// Set ground, ADC, DAC reference voltage (bits 8:4).
// be set to VDDA/2.
// The bias current should be set to 50% of the nominal value (bits 3:1)
Write CHIP_REF_CTRL
// Set LINEOUT reference voltage to VDDIO/2 (1.65V) (bits 5:0) and bias cur-
rent (bits 11:8) to the recommended value of 0.36mA for 10kOhm load with 1nF
capacitance
Write CHIP_LINE_OUT_CTRL
//----------------Other Analog Block Configurations------------------
// Configure slow ramp up rate to minimize pop (bit 0)
Write CHIP_REF_CTRL
// Enable short detect mode for headphone left/right
// and center channel and set short detect current trip level
This next 2 Write calls is needed ONLY if VDDD is
This next Write call is needed ONLY if VDDD is
The next 2 Write calls is needed only if both VDDA and
The next 2 modify calls is only needed if both VDDA and
The value written in the next 2 Write calls is dependent
Chip Powerup and Supply Configurations
The initialization sequence below assumes VDDIO = 3.3V and
This example assumes VDDA = 1.8V. VDDA/2 =
0x0008
0x7260
0x4260
0x0800
0x4A60
0x006C
0x004E
0x0322
0x004F
The value should
SGTL5000
0.9V.
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