EMC2101-R-ACZL-TR SMSC, EMC2101-R-ACZL-TR Datasheet - Page 17

• Manufacturer Part Number: EMC2101-R-ACZL-TR
• Description: Board Mount Temperature Sensors Single Fan Controller
• Manufacturer: SMSC

Specifications of EMC2101-R-ACZL-TR

• Full Temp Accuracy: +/- 2 C , +/- 3 C
• Package / Case: MSOP
• Output Type: Analog
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SMBus Fan Control with 1°C Accurate Temperature Monitoring
Datasheet
SMSC EMC2101
4.7
4.8
4.9
The EMC2101 will respond to the ARA in the following way when the ALERT / TACH pin is configured
as an Interrupt:
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
2. Set the MASK bit to clear the ALERT / TACH pin only if there are no bits set in the Status Register.
When the ALERT / TACH pin is configured to operate in Comparator Mode, or as a TACH input, (see
Section
the ARA command if the ALERT / TACH pin is not asserted.
The EMC2101 is addressed on the SMBus as 100_1100b.
Attempting to communicate with the EMC2101 SMBus interface with an invalid slave address or invalid
protocol will result in no response from the device and will not affect its register contents.
The EMC2101 includes an SMBus time-out feature. Following a 25ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface.
The EMC2101-R acts as a simple SMBus Master to read data from a connected EEPROM using the
following procedure:
1. After power-up the EMC2101-R waits for 10ms with the SMDATA and SMCLK pins tri-stated.
2. Once the wait period has elapsed, the EMC2101-R sends a START signal followed by the 7 bit
3. When the EEPROM sends the ACK signal, the EMC2101-R will send a second start signal and
4. Resets the device as an SMBus Client.
If the EMC2101-R does not receive an acknowledge bit from the EEPROM then the following will
occur:
1. The ALERT / TACH pin will be asserted and will remain asserted until a Host device initiates
2. The EMC2101-R will reset its SMBus protocol as a slave interface and start operating from the
SMBus Address
SMBus Time-out
Programming from EEPROM
from the device was not prematurely stopped due to a bus contention event).
If there are error condition bits set in the Status Register, it must be read before the MASK bit will
be set.
client address 101_0000b followed by a ‘1b’ and waits for an ACK signal from the EEPROM.
continue sending the Block Read Command (see
256 data bytes from the EEPROM sending an ACK between each data byte. When 256 data bytes
have been received, it sends a NACK signal followed by a STOP bit.
communication with the EMC2101 and reads the Status Register at offset 0x02. The ALERT /
TACH pin will be de-asserted after a single Status Register read, i.e. it is not sticky.
default conditions.
5.4.1), it will not respond to the ARA command. Additionally, the EMC2101 will not respond to
DATASHEET
17
Table
4.7) to the same slave address. It reads
Revision 2.54 (06-16-09)