MAX9853ETM+ Maxim Integrated Products, MAX9853ETM+ Datasheet - Page 48

• Manufacturer Part Number: MAX9853ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9853ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Conversion Rate: 48 KHz
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Snr: 75 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
1 = Master mode (LRCLK and BCLK timing signals
generated internally; LRCLK and BCLK configured as
outputs).
0 = Slave mode (LRCLK and BCLK accepted from
external source; LRCLK and BCLK configured as
inputs).
Slave mode timing signals may operate asynchronous
to either the MCLK or the other audio interface source
in DAC-only stereo audio modes. An interface with the
ADC output enabled must operate in master mode,
unless operating synchronously in voice mode.
1 = Right-channel data is transmitted while LRCLK is
low.
0 = Left-channel data is transmitted while LRCLK is
low.
Set S1WCI/S2WCI = 0 to conform to the I
S1WCI/S2WCI have no effect in voice mode.
1 = Digital audio bits are transferred on the falling edge
of BCLK.
0 = Digital audio bits are transferred on the rising edge
of BCLK.
Set S1BCI/S2BCI = 0 to conform to the I
1 = Digital audio MSB on SDIN and SDOUT is trans-
ferred on the 2nd BCLK edge following an LRCLK edge.
0 = Digital audio MSB on SDIN and SDOUT is trans-
ferred on the 1st BCLK edge following an LRCLK edge.
Set S1DLY/S2DLY = 1 to conform to the I
S1DLY/S2DLY have no effect in voice mode.
1 = 18-bit digital audio data.
0 = 16-bit digital audio data.
When operating in master mode, the number of BLCK
cycles per sample corresponds to the word size select-
ed by S1WS/S2WS. S1WS/S2WS have no effect in
voice mode.
Table 14. Digital Filter
48
REG
0x07
______________________________________________________________________________________
MHZ
B7
ADCDC ABPE DBPE
B6
Digital Filter Register (0x07)
B5
Master Mode (S1MAS/S2MAS)
LRCLK Invert (S1WCI/S2WCI)
BCLK Invert (S1BCI/S2BCI)
Data Delay (S1DLY/S2DLY)
Word Size (S1WS/S2WS)
B4
B3
DHPL
2
S standard.
B2
2
2
S standard.
S standard.
B1
DHPR
B0
MCLK Frequency Mode (MHz)
1 = 26MHz MCLK.
0 = 13MHz MCLK.
A 26MHz clock allows for synchronous 16kHz voice
mode. All other modes of operation can operate from
either MCLK frequency.
1 = ADC DC block enabled.
0 = ADC DC block disabled.
DC-blocking consists of a highpass filter with a cutoff
frequency of f
of operation including voice modes. The ADC DC-
blocking filter can be overloaded with low-frequency
signals with DC offset greater than ±0.125V (one-eighth
full scale).
1 = ADC bandpass filter enabled.
0 = ADC bandpass filter disabled.
ABPE = 1 enables the ADC highpass filter in combina-
tion with the ADC lowpass filter to create a bandpass
filter. The ADC voiceband filters only operate on the left
output channel data of voiceband, the ADC, and when
operating in voice mode.
1 = DAC bandpass filter enabled.
0 = DAC bandpass filter disabled.
DBPE = 1 enables the DAC highpass filter in combina-
tion with the DAC lowpass filter to create a bandpass
filter. The DAC filters only operate on the S1 left input or
mono S1 L+R input signal data.
00 = No filtering.
01 = 55Hz to 91Hz cutoff frequency.
10 = 171Hz to 279Hz cutoff frequency.
11 = 327Hz to 533Hz cutoff frequency.
When both the ADC and DAC are enabled, the exact
cutoff frequency of each setting depends on the sam-
ple rate in use. In DAC-only mode, the exact cutoff fre-
quency will be the high end of the range above.
Left and Right DAC Highpass Filter Mode
ADC DC-Blocking Filter Enable (ADCDC)
S
/ 1608. This filter is available in all modes
ADC Bandpass Filter Enable (ABPE)
DAC Bandpass Filter Enable (DBPE)
(DHPL/DHPR)