AD1838AS-REEL Analog Devices Inc, AD1838AS-REEL Datasheet
AD1838AS-REEL
Specifications of AD1838AS-REEL
Related parts for AD1838AS-REEL
AD1838AS-REEL Summary of contents
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FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports kHz Sample Rates 192 kHz Sample Rate Available on One DAC Supports 16-/20-/24-Bit Word Lengths Multibit - Modulators with Perfect Differential Linearity Restoration for ...
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AD1838–SPECIFICATIONS TEST CONDITIONS Supply Voltages ( Ambient Temperature Input Clock DAC Input Signal ADC Input Signal Input Sample Rate ( Measurement Bandwidth Word Width Load Capacitance Load Impedance Performance of all channels is ...
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Parameter ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple ...
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AD1838 TIMING SPECIFICATIONS Parameter MASTER CLOCK AND RESET t MCLK High MH t MCLK Low ML PD/RST Low t PDR SPI PORT t CCLK High CCH t CCLK Low CCL t CCLK Period CCP t CDATA Setup CDS t CDATA ...
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Parameter TDM256 MODE (Master) t BCLK Delay TBD t FSTDM Delay FSD t ASDATA Delay TABD t DSDATA1 Setup TDDS t DSDATA1 Hold TDDH TDM256 MODE (Slave) f BCLK Frequency AB t BCLK High TBCH t BCLK Low TBCL t ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model AD1838AS AD1838AS-REEL EVAL-AD1838EB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1838 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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DVDD CLATCH CIN PD/RST AGND OUTLN1 OUTLP1 OUTRN1 OUTRP1 AGND AVDD OUTLN2 OUTLP2 Pin No. Mnemonic 1, 39 DVDD 2 CLATCH 3 CIN PD/RST 4 5, 10, 16, 24, 30, 34 AGND 6, 12, 25 OUTLNx 7, 13, 26 OUTLPx ...
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AD1838–Typical Performance Characteristics 0 –50 –100 –150 0 5 FREQUENCY (Normalized to TPC 1. ADC Composite Filter Response 5 0 –5 –10 –15 –20 –25 – FREQUENCY (Hz) TPC 2. ADC High-Pass Filter Response –50 ...
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FREQUENCY (kHz) TPC 7. DAC Composite Filter Response, f 0.10 0.05 0 –0.05 –0. FREQUENCY (kHz) TPC 8. DAC Composite Filter Response, f (Pass-Band Section) REV. A 0.2 0.1 0 ...
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AD1838 TERMINOLOGY Dynamic Range The ratio of a full-scale input signal to the integrated input noise in the pass band ( kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and ...
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FUNCTIONAL OVERVIEW ADCs There are two ADC channels in the AD1838, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate kHz. The ADCs include on-board ...
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AD1838 To maintain the highest performance possible recommended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones ...
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CLS t CLATCH CCP CCLK CIN D15 D14 t COE COUT LRCLK LEFT CHANNEL BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK MSB SDATA LRCLK BCLK SDATA MSB NOTES 1. DSP MODE DOES NOT ...
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AD1838 t ABH ABCLK t ABL t ALS ALRCLK ASDATA LEFT-JUSTIFIED MSB MODE ASDATA MODE ASDATA RIGHT-JUSTIFIED MODE t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATA 2 I ...
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LRCLK BCLK ADC DATA LRCLK BCLK DAC DATA ABCLK ALRCLK ASDATA MSB Figure 9. ADC Packed Mode Timing REV. A 256 BCLKs 32 BCLKs SLOT 1 SLOT 5 SLOT 2 SLOT 3 SLOT 4 SLOT 6 LEFT RIGHT MSB MSB ...
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AD1838 Pin Name ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK(I/O) DBCLK (I)/AUXBCLK(I/O) DAUXDATA(O) FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) INTERNAL ASDATA ADC L1 32 MSB ...
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LRCLK BCLK ADC 1 SLAVE DATA MCLK LRCLK BCLK ADC 1 SLAVE DATA MCLK LRCLK BCLK ADC 2 SLAVE DATA MCLK Figure 12. Aux-Mode Connection to SHARC (Master Mode) LRCLK BCLK ADC 1 MASTER DATA MCLK LRCLK BCLK ADC 1 ...
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AD1838 CONTROL/STATUS REGISTERS The AD1838 has 13 control registers which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. ...
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Register Register Address Name 0000 DACCTRL1 0001 DACCTRL2 0010 DACVOL1 0011 DACVOL2 0100 DACVOL3 0101 DACVOL4 0110 DACVOL5 0111 DACVOL6 1000 RES 1001 RES 1010 ADCPeak0 1011 ADCPeak1 1100 ADCCTRL1 1101 ADCCTRL2 1110 ADCCTRL3 1111 Reserved Address R/W RES De-emphasis ...
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AD1838 Table VI. DAC Volume Control Address R/W RES DAC Volume 15, 14, 13 0010 = DACL1 0 0 0000000000 = Mute 0011 = DACR1 0000000001 = ...
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F 600Z 5.76k 5.76k AUDIO + INPUT 120pF NPO 100pF NPO OP275 V REF 5.76k 5.76k 750k OP275 V REF Figure 14. Typical ADC Input Filter Circuit REV. A 237 OUTLNx ADCxN 1nF NPO 100pF NPO 1nF OUTLPx NPO ...
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AD1838 SEATING PLANE VIEW A OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 13.45 1.03 13.20 SQ 2.45 0.88 12.95 MAX 0. 7.80 TOP VIEW REF (PINS DOWN) PIN 0.23 ...
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Revision History Location 8/03—Data Sheet changed from REV REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . ...
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