MCP2515-I/SO Microchip Technology, MCP2515-I/SO Datasheet - Page 41

• Manufacturer Part Number: MCP2515-I/SO
• Description: IC CAN CONTROLLER W/SPI 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2515-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 2.7V To 5.5V
• Driver Case Style: SOIC
• No. Of Pins: 18
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Supply Voltage Min: 2.7V
• Rohs Compliant: Yes
• Clock Frequency: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP2515DM-BM - BOARD DEMO FOR MCP2515/51MCP2515DM-PTPLS - BOARD DAUGHTER PICTAIL MCP2515MCP2515DM-PCTL - BOARD DEMO FOR MCP2515DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3
Some requirements for programming of the time
segments:
• Prop Seg + Phase Seg 1 >= Phase Seg 2
• Prop Seg + Phase Seg 1 >= T
• Phase Seg 2 > Sync Jump Width
For example, assuming that a 125 kHz CAN baud rate
with F
T
T
16 T
Typically, the sampling of the bit should take place at
about 60-70% of the bit time, depending on the system
parameters. Also, typically, the T
SyncSeg = 1 T
Seg 1 = 7 T
transition. This would leave 6 T
Since Phase Seg 2 is 6, according to the rules, SJW
could be a maximum of 4 T
typically only necessary when the clock generation of
the different nodes is inaccurate or unstable, such as
using ceramic resonators. So an SJW of 1 is usually
enough.
5.4
The bit timing requirements allow ceramic resonators
to be used in applications with transmission rates of up
to 125 kbit/sec, as a rule of thumb. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
OSC
Q
2003 Microchip Technology Inc.
= 500 nsec. To obtain 125 kHz, the bit time must be
Q
.
OSC
= 50 nsec, choose BRP<5:0> = 04h, then
Programming Time Segments
Oscillator Tolerance
= 20 MHz is desired:
Q
would place the sample at 10 T
Q
and Prop Seg = 2 T
Q
. However, a large SJW is
Q
DELAY
DELAY
for Phase Seg 2.
Q
. So setting Phase
is 1-2 T
Q
after the
Q
.
Preliminary
5.5
The configuration registers (CNF1, CNF2, CNF3)
control the bit timing for the CAN bus interface. These
registers can only be modified when the MCP2515 is in
configuration mode (see Section 9.0, “Modes of
Operation”).
5.5.1
The BRP<5:0> bits control the baud rate prescaler.
These bits set the length of T
input frequency, with the minimum T
Tosc (when BRP<5:0> = b’000000’). The SJW<1:0>
bits select the synchronization jump width in terms of
number of T
5.5.2
The PRSEG<2:0> bits set the length (in T
propagation segment. The PHSEG1<2:0> bits set the
length (in T
The SAM bit controls how many times the RXCAN pin
is sampled. Setting this bit to a ‘1’ causes the bus to be
sampled three times: twice at T
point and once at the normal sample point (which is at
the end of phase segment 1). The value of the bus is
determined to be the majority sampled. If the SAM bit
is set to a ‘0’, the RXCAN pin is sampled only once at
the sample point.
The BTLMODE bit controls how the length of phase
segment 2 is determined. If this bit is set to a ‘1’, the
length of phase segment 2 is determined by the
PHSEG2<2:0> bits of CNF3 (see Section 5.5.3,
“CNF3”). If the BTLMODE bit is set to a ‘0’ then the
length of phase segment 2 is the greater of phase
segment 1 and the information processing time (which
is fixed at 2 T
5.5.3
The PHSEG2<2:0> bits set the length (in T
phase segment 2, if the CNF2.BTLMODE bit is set to a
‘1’. If the BTLMODE bit is set to a ‘0’, the
PHSEG2<2:0> bits have no effect.
Bit Timing Configuration
Registers
Q
CNF1
CNF2
CNF3
Q
’s) of phase segment 1.
Q
’s.
for the MCP2515).
MCP2515
Q
Q
relative to the OSC1
/2 before the sample
DS21801B-page 41
Q
length being 2
Q
’s) of the
Q
’s) of