ENC28J60/SS Microchip Technology, ENC28J60/SS Datasheet - Page 25

IC ETHERNET CTRL 8K W/SPI 28SSOP

ENC28J60/SS

Manufacturer Part Number
ENC28J60/SS
Description
IC ETHERNET CTRL 8K W/SPI 28SSOP
Manufacturer
Microchip Technology
Datasheets

Specifications of ENC28J60/SS

Package / Case
28-SSOP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.1 V to 3.6 V
Supply Current (max)
180 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ENC28J60/SS
Manufacturer:
MICROCHIP
Quantity:
6 500
Part Number:
ENC28J60/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
REGISTER 3-5:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Read-only bit
-n = Value at POR
bit 15-13
bit 12
bit 11
bit 10-3
bit 2
bit 1
bit 0
U-0
U-0
Unimplemented: Read as ‘0’
PFDPX: PHY Full-Duplex Capable bit
1 = PHY is capable of operating at 10 Mbps in Full-Duplex mode (this bit is always set)
PHDPX: PHY Half-Duplex Capable bit
1 = PHY is capable of operating at 10 Mbps in Half-Duplex mode (this bit is always set)
Unimplemented: Read as ‘0’
LLSTAT: PHY Latching Link Status bit
1 = Link is up and has been up continously since PHSTAT1 was last read
0 = Link is down or was down for a period since PHSTAT1 was last read
JBSTAT: PHY Latching Jabber Status bit
1 = PHY has detected a transmission meeting the jabber criteria since PHSTAT1 was last read
0 = PHY has not detected any jabbering transmissions since PHSTAT1 was last read
Unimplemented: Read as ‘0’
U-0
U-0
PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1
‘1’ = Bit is set
‘0’ = Bit is cleared
R/L = Read-only latch bit
U-0
U-0
PFDPX
R-1
U-0
Preliminary
U = Unimplemented bit, read as ‘0’
LL = Bit latches low
PHDPX
R-1
U-0
LLSTAT
R/LL-0
U-0
LH = Bit latches high
ENC28J60
JBSTAT
R/LH-0
U-0
DS39662C-page 23
U-0
U-0
bit 8
bit 0

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