KSZ8873MLL Micrel Inc, KSZ8873MLL Datasheet - Page 17
![IC ETHERNET SWITCH 3PORT 64-LQFP](/photos/6/81/68149/64-lqfp-micrel_sml.jpg)
KSZ8873MLL
Manufacturer Part Number
KSZ8873MLL
Description
IC ETHERNET SWITCH 3PORT 64-LQFP
Manufacturer
Micrel Inc
Specifications of KSZ8873MLL
Data Rate
100Mbps
Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
No. Of Ports
3
Ethernet Type
IEEE 802.3u
Supply Current
115mA
Supply Voltage Range
2.5V, 3.3V
Digital Ic Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (15-Dec-2010)
Base
RoHS Compliant
Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Fiber Support
No
Integrated Led Drivers
Yes
Phy/transceiver Interface
MII
Power Supply Type
Analog/Digital
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Temperature Classification
Commercial
Interface Type
MII, RMII
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-3459
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8873MLL
Manufacturer:
Micrel Inc
Quantity:
1 934
Company:
Part Number:
KSZ8873MLL
Manufacturer:
ADI
Quantity:
27
Company:
Part Number:
KSZ8873MLL AM
Manufacturer:
Micrel
Quantity:
1 638
Company:
Part Number:
KSZ8873MLLJ
Manufacturer:
Micrel
Quantity:
323
Micrel, Inc.
KSZ8873MLL/FLL/RLL
Functional Description
The KSZ8873MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer
2 managed switch.
The KSZ8873MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design,
the host processor has complete control of the KSZ8873MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or
2
I
C bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
On the media side, the KSZ8873MLL/FLL/RLL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an
external1% 11.8KΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8873MLL/FLL/RLL generates 125MHz, 62.5MHz, and 31.25MHz clocks for system timing. Internal clocks are
generated from an external 25MHz or 50MHz crystal or oscillator. KSZ8873RLL can generates a 50MHz reference clock
for the RMII interface
Scrambler/De-scrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
100BASE-FX Operation
100BASE-FX operation is similar to 100BASE-TX operation with the differences being that the scrambler/de-scrambler
and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is bypassed and
auto MDI/MDI-X is disabled.
September 2009
17
M9999-092309-1.2