KSZ8842-16MQL Micrel Inc, KSZ8842-16MQL Datasheet - Page 18

• Manufacturer Part Number: KSZ8842-16MQL
• Description: IC SWITCH 10/100 16BIT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8842-16MQL

• Data Rate: 100Mbps
• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u
• Supply Current: 122mA
• Supply Voltage Range: 3.1V To 3.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: QFP
• No. Of: RoHS Compliant
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Interface Type: PCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1634 - BOARD EVALUATION KSZ8842-16MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1478-5

Micrel Confidential
November 2005
Pin
Number
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Pin Name
BCLK
DATACSN
NC
SRDYN
INTRN
LDEVN
RDN
EECS
ARDY
CYCLEN
P2LED3
DGND
VDDCO
VLBUSN
EEEN
Type
Ipd
Ipu
Opu
Opu
Opd
Opd
Ipd
Opu
Opd
Ipd
Opd
Gnd
P
Ipd
Ipd
Pin Function
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This pin should be tied Low or unconnected if it is in asynchronous mode.
DATA Chip Select Not (For KSZ8842-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
When DATACSN is Low, the data path can be accessed regardless of the value of
AEN, A15-A1, and the content of the BANK select register.
No connect.
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-like
extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal is
synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8842M drives this pin low to signal
wait states.
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need
an external 4.7K pull-up resistor.
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8842M address programmed into the high byte of the base address register.
LDEVN is a combinational decode of the Address and AEN signal.
Read Strobe Not
Asynchronous read strobe, active Low.
EEPROM Chip Select
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access
cycles. It is asynchronous to the host CPU or bus clock.
Cycle Not
For VLBus-like mode cycle signal; this pin follows the addressing cycle to signal the
command cycle.
For burst mode (32-bit interface only), this pin stays High for read cycles and Low for
write cycles.
Port 2 LED indicator.
See the description in pins 6, 7, and 8.
Digital IO ground
1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V
output pin provides power to VDDC, VDDA and VDDAP pins.
Note: Internally generated power voltage. Do not connect an external power supply to
this pin. This pin is used for connecting external filter (Ferrite Bead and capacitors).
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 32-bit asynchronous mode or EISA-like burst
mode.
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
18
KSZ8842-16/32 MQL/MVL
Rev. 1.4