MCP2515-E/ST Microchip Technology, MCP2515-E/ST Datasheet - Page 37
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MCP2515-E/ST
Manufacturer Part Number
MCP2515-E/ST
Description
IC CAN CONTROLLER W/SPI 20TSSOP
Manufacturer
Microchip Technology
Specifications of MCP2515-E/ST
Package / Case
20-TSSOP
Controller Type
CAN Interface
Interface
SPI
Voltage - Supply
2.7 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
Controller Area Network (CAN)
Number Of Transceivers
1
Data Rate
1 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Ic Interface Type
SPI
No. Of Tx Buffers
3
No. Of Rx Buffers
2
No. Of Filters
6
No. Of Masks
2
No. Of Interrupts
1
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
TSSOP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP2515DM-BM - BOARD DEMO FOR MCP2515/51MCP2515DM-PTPLS - BOARD DAUGHTER PICTAIL MCP2515MCP2515DM-PCTL - BOARD DEMO FOR MCP2515DV251001 - KIT DEVELOPMENT CAN MCP2510
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP2515-E/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
5.0
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non Return to
Zero (NRZ) coding, which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission times may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data
transmission edges to synchronize and maintain the
receiver clock. Since the data is NRZ-coded, it is
necessary to include bit-stuffing to ensure that an edge
occurs at least every six bit times to maintain the Digital
Phase Lock Loop (DPLL) synchronization.
The bit timing of the MCP2515 is implemented using a
DPLL that is configured to synchronize to the incoming
data, and provide the nominal timing for the transmitted
data. The DPLL breaks each bit time into multiple
segments made up of minimal periods of time, called
the Time Quanta (TQ).
Bus timing functions executed within the bit time frame
(such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning) are defined by the programmable bit timing
logic of the DPLL.
FIGURE 5-1:
2004 Microchip Technology Inc.
SyncSeg
BIT TIMING
CAN BIT TIME SEGMENTS
PropSeg
Nominal Bit Time (NBT), t
Preliminary
PhaseSeg1 (PS1)
5.1
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the baud
rate prescaler and number of time quanta in each
segment.
The CAN bit time is made up of non-overlapping
segments. Each of these segments are made up of
integer units called Time Quanta (TQ), explained later
in this data sheet. The Nominal Bit Rate (NBR) is
defined in the CAN specification as the number of bits
per second transmitted by an ideal transmitter with no
resynchronization. It can be described with the
equation:
EQUATION 5-1:
Nominal Bit Time
The Nominal Bit Time (NBT) (t
overlapping segments (Figure 5-1). Therefore, the
NBT is the summation of the following segments:
Associated with the NBT are the sample point,
Synchronization Jump Width (SJW) and Information
Processing Time (IPT), which are explained later.
SYNCHRONIZATION SEGMENT
The Synchronization Segment (SyncSeg) is the first
segment in the NBT and is used to synchronize the
nodes on the bus. Bit edges are expected to occur
within the SyncSeg. This segment is fixed at 1 TQ.
t bit
bit
The CAN Bit TIme
=
t SyncSeg
Sample
Point
NBR
+
=
PhaseSeg2 (PS2)
t PropSeg
f bit
MCP2515
=
bit
------ -
t
) is made up of non-
bit
1
+
t PS1
DS21801C-page 37
+
t PS2