UJA1076TW/5V0/WD,1 NXP Semiconductors, UJA1076TW/5V0/WD,1 Datasheet - Page 9

• Manufacturer Part Number: UJA1076TW/5V0/WD,1
• Description: IC SBC CAN HS 5V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1076TW/5V0/WD,1

• Controller Type: System Basis Chip
• Interface: SPI
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 82µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
UJA1076_2
Product data sheet
6.1.4 Normal mode
6.1.5 Sleep mode
6.1.6 Overtemp mode
Normal mode is selected from Standby mode by setting bits MC in the Mode_Control
register
In Normal mode, the CAN physical layer will be enabled (Active mode; STBCC = 0; see
Table
detection active.
The SBC will exit Normal mode if:
Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the
Mode_Control register
no pending interrupts (INTN = HIGH) or wake-up events and at least one wake-up source
is enabled (CAN or WAKE). Any attempt to enter Sleep mode while one of these
conditions has not been satisfied will result in a short reset (3.6 ms minimum pulse width;
see
In Sleep mode, V1 and V2 are off and the CAN transceiver will be switched off (Off mode;
STBCC = 0; see
wake-up detection active - see
LOW.
A CAN or local wake-up event will cause the SBC to switch from Sleep mode to Standby
mode, generating a (short or long; see
control bits (MC) will be changed to 00 and V1 will be enabled.
The SBC will enter Overtemp mode from Normal mode or Standby mode when the chip
temperature exceeds the overtemperature protection activation threshold, T
In Overtemp mode, the voltage regulators are switched off and the bus system is in a
high-resistive state. When the SBC enters Overtemp mode, the RSTN pin is driven LOW
and the limp home control bit, LHC, is set so that the LIMP pin is driven LOW.
The chip temperature must drop a hysteresis level below the overtemperature shutdown
threshold before the SBC can exit Overtemp mode. After leaving Overtemp mode the
SBC enters Standby mode and a system reset is generated (reset pulse width of t
long or short; see
•
•
•
•
Standby mode is selected by setting bits MC to 00
Sleep mode is selected by setting bits MC to 01
A system reset is generated (see
The chip temperature rises above the OTP activation threshold, T
SBC to switch to Overtemp mode
Section 6.5.1
6) or in a low-power state (Lowpower mode; STBCC = 1) with bus wake-up
(Table
5) to 10 (V2 disabled) or 11 (V2 enabled).
All information provided in this document is subject to legal disclaimers.
Table
and
Section 6.5.1
Table
(Table
6) or in a low-power state (Lowpower mode; STBCC = 1) with bus
Rev. 02 — 27 May 2010
11).
5) to 01. The SBC will enter Sleep mode providing there are
Section
and
Table
Section
Section
6.7.1). The watchdog is off and the reset pin is
11).
6.1.3; the SBC will enter Standby mode)
High-speed CAN core system basis chip
6.5.1) system reset. The value of the mode
th(act)otp
UJA1076
© NXP B.V. 2010. All rights reserved.
th(act)otp
, causing the
w(rst)
,
9 of 47
,