VNC2-32L1B-REEL FTDI, Future Technology Devices International Ltd, VNC2-32L1B-REEL Datasheet - Page 42
![IC USB HOST VINCULUM-II 32LQFN](/photos/6/82/68259/ftdi_vinculum_vnc2_sml.jpg)
VNC2-32L1B-REEL
Manufacturer Part Number
VNC2-32L1B-REEL
Description
IC USB HOST VINCULUM-II 32LQFN
Manufacturer
FTDI, Future Technology Devices International Ltd
Series
Vinculum-IIr
Datasheet
1.VNC2-32Q1B-REEL.pdf
(90 pages)
Specifications of VNC2-32L1B-REEL
Mfg Application Notes
Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote
Controller Type
USB 2.0 Controller
Interface
SPI Serial, USB, UART
Voltage - Supply
1.62 V ~ 1.98 V
Current - Supply
25mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
768-1051-2
VNC2-32L1A-REEL
VNC2-32L1A-REEL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
VNC2-32L1B-REEL
Manufacturer:
FTDI, Future Technology Devices International Ltd
Quantity:
10 000
Part Number:
VNC2-32L1B-REEL
Manufacturer:
FTDI
Quantity:
20 000
6.2.1 SPI Clock Phase Modes
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known
as Mode 0, Mode 1, Mode 2 and Mode 3. Table 16 summarizes these modes and available interface and
Figure 6-3 is the function timing diagram.
For CPOL = 0, the base (inactive) level of SCLK is 0.
In this mode:
For CPOL =1, the base (inactive) level of SCLK is 1.
In this mode:
Mode
Table 16 - Clock Phase/Polarity Modes
Figure 6-3 - SPI CPOL CPHA Function
0
1
2
3
CPOL
0
0
1
1
• When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
• When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
• When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the
rising edge of SCLK
• When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
CPHA
0
1
0
1
Copyright © 2010 Future Technology Devices International Limited
Duplex
Full
N
N
Y
Y
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Duplex
4 pin
Half
N
Y
N
Y
Duplex
3 pin
Half
N
Y
N
Y
Unmanged
Y
Y
Y
Y
Legacy
VNC1L
N
N
N
N
Document No.: FT_000138
Clearance No.: FTDI#
Version -
143
1.2
42