Z16C3010VEG Zilog, Z16C3010VEG Datasheet
Z16C3010VEG
Specifications of Z16C3010VEG
Z16C3010VEG
Available stocks
Related parts for Z16C3010VEG
Z16C3010VEG Summary of contents
Page 1
... Z16C30 USC User’s Manual UM009402-0201 ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com ...
Page 2
... Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded ...
Page 3
... Z ILOG Z16C30 USC Thank you for your interest in Zilog's high-speed Integrated Universal Serial Controller. To aid the designer, the following support material is available when designing a High Performance Serial Communication application based on Zilog's USC. Z16C30 User's Manual ® Zilog's USC User's Manual is a comprehensive break- down of the functions and features of the USC which will aid in the development of your application ...
Page 4
... The kit also contains software and documentation to sup- port software and hardware development for Zilog's USC. © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice ...
Page 5
Z ILOG Z16C30 USC HAPTER ITLE AND Chapter 1 Introduction 1.1 Introduction ....................................................................................................... 1-1 1.2 Features ............................................................................................................. 1-1 1.3 Logic Symbol ..................................................................................................... 1-2 1.4 Packaging ......................................................................................................... 1-3 1.5 Overview of the USC and this Manual ............................................................... 1-4 ...
Page 6
Z ILOG HAPTER ITLE AND Chapter 3 A Sample Introduction 3.1 Introduction ....................................................................................................... 3-1 Chapter 4 Serial Interfacing 4.1 Introduction ....................................................................................................... 4-1 4.2 Serial Interface Pin Descriptions ....................................................................... 4-1 4.3 Transmit and Receive Clocking ........................................................................ 4-2 4.3.1 ...
Page 7
Z ILOG HAPTER ITLE AND 5.15 HDLC/SDLC Loop Mode ................................................................................. 5-21 5.16 Cyclic Redundancy Checking ......................................................................... 5-22 5.17 Parity Checking ............................................................................................... 5-25 5.18 Status Reporting .............................................................................................. 5-26 5.18.1 Detailed Status in the TCSR ................................................................. 5-28 5.18.2 Detailed ...
Page 8
Z ILOG HAPTER ITLE AND Chapter 7 Interrupts 7.1 Introduction ....................................................................................................... 7-1 7.2 Interrupt Acknowledge Daisy-Chains ................................................................ 7-1 7.3 External Interrupt Control Logic ........................................................................ 7-2 7.4 Using /RxReq and /TxReq as Interrupt Requests ............................................. 7-3 7.5 Interrupt ...
Page 9
Z ILOG HAPTER ITLE AND Appendix A Appendix Changes A.1 Introduction ............................................................................................................ A-1 A.1.1 Transmit Status Blocks/Transmit Control Blocks .................................... A-1 A.1.2 Interrupt Enable (for Individual Sources) Interrupt Arm ......................... A-1 A.2 Commands ........................................................................................................ A-1 A.2.1 Reload ...
Page 10
Z ILOG F T IGURE ITLES Chapter 1 Figure 1-1. USC Logic Symbol ................................................................................. 1-2 Figure 1-2. USC 68-pin PLCC Pinout ........................................................................ 1-3 Figure 1-3. USC Block Diagram .............................................................................. 1-11 Chapter 2 Figure 2-1. Simple Multiplexed System .................................................................... 2-1 Figure ...
Page 11
Z ILOG F T IGURE ITLES Chapter 5 Figure 5-1. Asynchronous Data ................................................................................ 5-2 Figure 5-2. Character Oriented Synchronous Data .................................................. 5-2 Figure 5-3. HDLC/SDLC Data ................................................................................... 5-4 Figure 5-4. The Channel Mode Register (CMR) ....................................................... 5-6 Figure 5-5. The ...
Page 12
Z ILOG F T IGURE ITLES Chapter 7 Figure 7-1. An Interrupt Daisy Chain ........................................................................ 7-2 Figure 7-2. External Interrupt Control ........................................................................ 7-3 Figure 7-3. USC Interrupt Types & Sources ............................................................. 7-5 Figure 7-4. A Model of the Interrupt Logic ...
Page 13
... USC Registers, in Address Order ........................................................ 2-12 Table 2-2. USC Registers, in Alphabetical Order .................................................. 2-13 © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc ...
Page 14
... Z ILOG 1.1 INTRODUCTION The Universal Serial Controller (USC tion successor to Zilog’s popular SCC family of multi- protocol serial controllers, and is recommended for new designs. Compared to the SCC family and most compet- ing devices, the USC features more serial protocols, a 16- or 8-bit data bus, higher data rates, larger FIFOs, better support for DMA operation, and more convenient software 1 ...
Page 15
Z ILOG 1.3 LOGIC SYMBOL 1-2 VDD /RESET /CS A//B D//C /AS R//W /DS /RD /WR Z16C30 /SITACK USC /PITACK IEIA, B /RxACKA,B /TxACKA,B /RxCA,B /TxCA,B RxDA,B /CTSA,B /DCDA,B VSS Figure 1-1. USC Logic Symbol UM009402-0201 AD15-AD0 /WAIT//RDY /INTA,B IEOA,B ...
Page 16
Z ILOG 1.4 PACKAGING /RxACKA /INTA 11 12 IEIA 13 IEOA 14 VSS 15 VDD 16 AD0 17 AD1 AD2 18 AD3 19 AD4 20 AD5 21 AD6 22 AD7 23 VSS 24 VDD 25 /RxREQA ...
Page 17
Z ILOG 1.5 OVERVIEW OF THE USC AND THIS MANUAL The following descriptions and Tables should be helpful in initial evaluation of the USC ® and in finding your way around this document. Subjects in the Tables are arranged in ...
Page 18
Z ILOG Table 1-1 Bus Interfacing Features of the USC (Chapter 2) Multiplexed or Separate Address and Data Bus(es) Read/Write Control Signals 8- or 16-Bit Data Bus Ready, Wait, or Acknowledge Handshaking Interrupt Acknowledge Cycles Direct or Indirect Register Addressing ...
Page 19
Z ILOG 1.5.6 Software Summary (Continued) Table 1-2. Serial Interfacing Features of the USC (Chapter 4) Clock Selection Clock Output CTR0, CTR1 Baud Rate Generators Digital-Phase Locked Loop Data Encoding Echoing and Looping Modem Controls and Interrupts DMA Controller Interface ...
Page 20
Z ILOG Table 1-3. Serial Controller Features of the USC Major Protocol Categories Asynchronous Protocols Character-Oriented Synchronous Protocols Bit-Oriented Synchronous Protocols Character Length CRC Generation/Checking Parity Checking Transmit Status Reporting Receive Status Reporting Character Counters RCC FIFO UM97USC0100 Chapter 4 ...
Page 21
Z ILOG Table 1-4. More Serial Controller Features of the USC Transmit Control Blocks Receive Status Blocks Commands Software Reset Rx and Tx FIFO Storage Between Frames/Messages Waiting for Software Response 1-8 UM009402-0201 A Transmit DMA channel can fetch the ...
Page 22
Z ILOG Flowthrough or Flyby DMA Requests Separating Receive Frames UM97USC0100 Table 1-5. DMA Features of the USC The USC can be used with DMA controllers in a “flowthrough” mode, in which the REQ line from the USC tells the ...
Page 23
... Non-Acknowledging Buses 1-10 Table 1-6. Interrupt Features of the USC was one of Zilog’s original contributions to microprocessor architecture. On the USC its use (to determine which of several interrupting devices to service first) is optional, and performance is much improved compared to older devices. can be used instead of a daisy chain to implement interrupt priority schemes other than strict priority, such as “ ...
Page 24
Z ILOG Bus Host Interface Processor DMA Controller, System Memory UM97USC0100 DPLL Counters BRG0, BRG1 Transmitter Serial Clock Logic Transmit FIFO Interrupt Control Interrupt Control Transmit FIFO Serial Clock Logic Transmitter DPLL Counters BRG0, BRG1 ® Figure 1-3. USC Block ...
Page 25
Z ILOG 1.6 DEVICE STRUCTURE Figure 1-1 shows the basic structure of the USC. The Bus Interface module stands between the external bus pins and an on-chip 16-bit data bus that interconnects the other functional modules. It includes several flexible ...
Page 26
... Chapter 8 then reviews the general programming model and includes a concise description of each register bit and field for quick reference. © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice ...
Page 27
... This section de- scribes how to use these facilities to interface the USC to a variety of host microprocessors and buses. same as that used on the host bus (as with a Zilog 16C0x), then the USC’s /AS pin can be directly connected to the corresponding bus signal. Figure 2-1 shows such a sys- tem ...
Page 28
Z ILOG 2.2 MULTIPLEXED/NON-MULTIPLEXED OPERATION (Continued) An 80x86-based system differs only in that the processor’s ALE signal has to be inverted to produce /AS for the USC. Figures 2-2 and 2-3 illustrate two ways to interface the USC to a ...
Page 29
Z ILOG 2.3 READ/WRITE DATA STROBES Another difference among host buses is the way in which read and write cycles are signalled and differentiated. Figures 2-4 and 2-5 show two standard methods sup- ported by the USC. In Figure 2-4, ...
Page 30
Z ILOG 2.4 BUS WIDTH Another major difference among host buses is the number of data bits that can be transferred in one cycle. Software can configure the USC to transfer 16 bits at a time, in which case it ...
Page 31
Z ILOG RD* or WR* or DS* WAIT* ACK* Ready Figure 2-6. A Fast and Slow Cycle, with Three Kinds of Handshaking 2.6 PIN DESCRIPTIONS /RESET. Reset (input, active low). A low on this line places the USC in a ...
Page 32
... BCR write. If A//B is high when the BCR is written, this line operates thereafter as a Ready/Wait line for Zilog and some Intel processors. In this mode the USC asserts this line low until it’s ready to complete an interrupt acknowledge cycle, but it never asserts this line when the host accesses one of the USC registers ...
Page 33
Z ILOG 2.7 PULL-UP RESISTORS AND UNUSED PINS All unused input pins should be pulled up, either by connecting them directly to Vcc or with a resistor. This may include /PITACK, /SITACK, IEI, and /ABORT. Bi-directional pins should typically be ...
Page 34
Z ILOG 2.8.2 Bits and Fields in the BCR (Continued) 16-Bit (BCR2): this bit should be written as 1 when the host data bus is 16 bits wide (or wider). Writing this bit as 0 has two effects: it restricts ...
Page 35
Z ILOG 2.9.3 Direct Register Addressing on AD6-AD0/AD7-AD1 If the USC samples D//C low, SepAd (BCR15 and the USC detected activity on /AS before or as the BCR was written, the USC samples the low-order AD pins to ...
Page 36
Z ILOG 2.9.5 About the Register Address Tables Tables 2-1 and 2-2 show the names and addresses of the addressable registers in the USC, in address and alpha- betical order. The Tables assume that SRightA (BCR0 The RegAddr ...
Page 37
Z ILOG Start: Host Cycle with /CS Low - which register to R/W? SEPAD (BCR15) 1 (Separate Addr) Activity on /AS after Reset? (Mux'ed Bus) No (Non-Mux'ed Bus) Capture iA//B:=A//B, RegAd = AD13-AD8, iD/C = D//C at fall of /DS, ...
Page 38
Z ILOG 2.9 Register Addressing (Continued) Register Name Acronym Channel Command/Address CCAR Channel Mode CMR Channel Command/Status CCSR Channel Control CCR Test Mode Data TMDR Test Mode Control TMCR Clock Mode Control CMCR Hardware Configuration HCR Interrupt Vector IVR Input/Output ...
Page 39
Z ILOG Table 2-2. USC Registers, in Alphabetical Order Register Name Acronym Channel Command/Address CCAR Channel Command/Status CCSR Channel Control CCR Channel Mode CMR Clock Mode Control CMCR Daisy-Chain Control DCCR Hardware Configuration HCR Input/Output Control IOCR Interrupt Control ICR ...
Page 40
... Tables 2-1 and 2-2 show RDR at the lower address and TDR at the higher one. The MSBytes of RDR and TDR should never be read or written alone, only as part of a 16-bit access Zilog 16C0x or Motorola 680x0 system, use direct addresses 97 or 113 ( hex) for channel B, and 225 or 241 ( hex) for channel A, to select the LSByte for byte transfers ...
Page 41
Z ILOG ADnn A//B, D//C /CS /SITACK /PITACK,/WR,(/RD OR /DS), DMA Acknowledge signals /AS R//W /DS or /RD /WAIT//RDY Figure 2-10. A Register Read Cycle with Multiplexed Addresses and Data UM97USC0100 Data Address UM009402-0201 Z16C30 USC ® ...
Page 42
Z ILOG 2.9.7 Register Read and Write Cycles (Continued) ADnn A//B, D//C /CS /SITACK /PITACK, /RD,(/WR or /DS), DMA Acknowledge signals /AS R//W /DS or /WR /WAIT//RDY Figure 2-11. A Register Write Cycle with Multiplexed Addresses and Data 2-16 Address ...
Page 43
Z ILOG ADnn A//B, D//C /CS /SITACK /PITACK, /WR, (/RD OR /DS), DMA Acknowledge signals R//W /DS or /RD /WAIT//RDY Figure 2-12. A Register Read Cycle with Non-Multiplexed Data Lines UM97USC0100 Data UM009402-0201 Z16C30 USC SER S ...
Page 44
... Figure 2-13. A Register Write Cycle with Non-Multiplexed Data Lines © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc ...
Page 45
Z ILOG 3.1 INTRODUCTION Figures 3-1 and 3-2 are schematics of a simple USC application. It includes a USC, an 80186 integrated pro- cessor, two EPROMs, two static RAMs, and 3 serial inter- faces. Figure 3-1 includes everything but the ...
Page 46
Z ILOG 3.1 INTRODUCTION (Continued) 3-2 UM009402-0201 ® Z16C30 USC SER S ANUAL UM97USC0100 ...
Page 47
Z ILOG UM97USC0100 UM009402-0201 ® Z16C30 USC SER S ANUAL 3-3 ...
Page 48
Z ILOG 3.1 INTRODUCTION (Continued) U7-9 are octal latches that capture the address from the 186 and present the latched address to the RAMs and EPROMs. The EPROMs are selected by the Upper Chip Select (/UCS) output of the 186, ...
Page 49
... Z ILOG © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc ...
Page 50
Z ILOG 4.1 INTRODUCTION ® The USC includes several serial interface options and features that promote its usefulness in various kinds of applications. It allows a variety of clocking schemes, and will do serial encoding and decoding for NRZI and ...
Page 51
Z ILOG 4.3 TRANSMIT AND RECEIVE CLOCKING The USC’s Receiver and Transmitter logic have separate internal clock signals that we’ll call RxCLK and TxCLK. In most of the USC’s operating modes, the Receiver samples a new bit on RxD once ...
Page 52
Z ILOG UM97USC0100 UM009402-0201 ® Z16C30 USC SER S ANUAL 4-3 ...
Page 53
Z ILOG 4.3.2 The Baud Rate Generators (Continued) CTR1Src CTR0Src BRG1Src Figure 4-2. The Clock Mode Control Register (CMCR) CTR1 CTR0Div CVOK DPLLDiv DSel Figure 4-3. The Hardware Configuration Register ...
Page 54
Z ILOG The output of either Baud Rate Generator can be used as RxCLK and/or TxCLK. It can be used as the reference clock input to the Digital Phase Locked Loop (DPLL) circuit, and it can be output on the ...
Page 55
Z ILOG 4.3.5 Clocking for Asynchronous Mode For asynchronous reception, transitions on RxCLK don’t have to have any relationship to transitions on RxD. When the Receiver is searching for a start bit, it samples RxD in each cycle of RxCLK, ...
Page 56
Z ILOG 4.4 DATA FORMATS AND ENCODING The USC’s Transmitter and Receiver can handle data in any of the eight formats shown in Figure 4-4. The RxDecode field in the Receive Mode Register (RMR15-13) controls the format for the Receiver, ...
Page 57
Z ILOG 4.4 DATA FORMATS AND ENCODING (Continued) In NRZI-Mark mode, at the start of each bit cell the transmitter inverts TxD for a 1 but leaves it unchanged for NRZI-Space mode, at the start of each ...
Page 58
Z ILOG In the Bi-phase-Level and Differential Bi-phase-Level encodings, there is always a transition at the midpoint of each active data bit, and there may or may not be transi- tions at the boundaries between bit cells. The DPLL gen- ...
Page 59
Z ILOG 4.5 MORE ABOUT THE DPLL (Continued) After software sets up the DPLL, three bits in the Channel Command/Status Register (CCSR) provide the operating interface. The logic enters a “fast sync mode” when soft- ware writes ...
Page 60
Z ILOG The RTMode field of the Channel Command/Address register (CCAR9-8) controls the relationship between the Transmitter and the Receiver and thus between the TxD and RxD pins encoded as follows: RTMode Operation 00 Normal operation: the Transmitter ...
Page 61
Z ILOG 4.7 EDGE DETECTION AND INTERRUPTS (Continued) RxCDn RxCUp TxCDn TxCUp RxRDn Figure 4-7. The Status Interrupt Control Register (SICR) RxCL/U /RxC TxCL/U /TxC RxRL/U /RxREQ ...
Page 62
Z ILOG 4.8 THE /DCD PIN The DCDMode field of the I/O Control Register (IOCR13- 12) controls the function of this pin: DCDMode Function of the /DCD pin 00 Low-active Rx Carrier input 01 Low-active Rx Sync input 10 Low ...
Page 63
Z ILOG 4.8 THE /DCD PIN (Continued) /DCD RxCLK (/RxC) RxD (Async, 9-Bit ACV/1553B RxD (Isochronous) RxD (External Sync) RxD (Monosync, Bisync, Transparent Bisync) RxD (HDLC) Software can program a channel to interrupt the host processor on either or both ...
Page 64
Z ILOG 4.9 THE /CTS PIN The CTSMode field of the I/O Control Register (IOCR15- 14) controls the function of this pin: CTSMode Function of the /CTS pin 0x Low-active Clear to Send input 10 Low output 11 High output ...
Page 65
Z ILOG 4.10 THE /RXC AND /TXC PINS Figure 4-1 shows each channel’s options for the function of its /RxC and /TxC pins. The RxCMode field in the Input/ Output Control Register (IOCR2-0) controls the function of /RxC: RxCMode Function ...
Page 66
Z ILOG 4.11 THE /RXREQ AND /TXREQ PINS The RxRMode and TxRMode fields of the I/O Control Register (IOCR9-8 and IOCR11-10 respectively) control the function of these pins: XxRMode Function of /XxREQ pin 00 Input pin 01 DMA Request output ...
Page 67
... Z ILOG © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc ...
Page 68
... This, in turn, makes for more flexible and ca- pable products for Zilog’s customers. This chapter de- 5.2 ASYNCHRONOUS MODES Figure 5-1 shows how a "start bit" precedes each character in async communications, and that so-called "stop bits" ...
Page 69
Z ILOG 5.2 ASYNCHRONOUS MODES (Continued) Start Bit 1/2 Bit Time Receiver detects Falling Edge Receiver validates Start Bit SYN STX STX (16) (16) (02) Figure 5-2. Character Oriented Synchronous Data 5 Data Bits, Plus Optional Parity ...
Page 70
Z ILOG 5.3 CHARACTER ORIENTED SYNCHRONOUS MODES These protocols came into use after async effort to get better line utilization by eliminating start and stop bits. In sync modes, characters follow one another directly on the serial link, ...
Page 71
Z ILOG 5.4 BIT ORIENTED SYNCHRONOUS MODES As character-oriented synchronous protocols came into wider use in the 1960’s and 70’s, the number of characters having special significance for the hardware kept increas- ing. Hand in hand with this, the complexity ...
Page 72
... Slaved Monosync 1101 — 1110 HDLC/SDLC Loop 1111 — Zilog reserves values shown above as “—” for future use; they should not be programmed in the indicated field. UM009402-0201 ® Z16C30 USC SER S ANUAL RxMode (CMR3-0) ...
Page 73
Z ILOG 5.5 THE MODE REGISTERS (CMR, TMR AND RMR) (Continued) Later sections describe each of these modes and proto- cols individually, including the significance of the Tx and RxSubMode bits (CMR15-12 and CMR7-4 respectively) in each case. The various ...
Page 74
Z ILOG 5.5.1 Enabling and Disabling the Receiver and Transmitter The TxEnable and RxEnable fields (TMR1-0 and RMR1- 0) enable and disable the Transmitter and Receiver to send and receive serial data TxEnable disables the Transmitter, so that ...
Page 75
Z ILOG 5.5.2 Character Length (Continued) When RxLength is less than eight in synchronous modes including HDLC/SDLC, the Receiver fills out the more significant bits of each byte with the last received bit (the parity bit if one is used), ...
Page 76
... Receiver, so that the same source can be used for both RxCLK and TxCLK. (See Chapter 4 for more information about clock selection.) Zilog reserves the two MSbits of the RxSubMode field (CMR7-6) in Asynchronous mode for use in future prod- ucts. They should always be programmed as 00. ...
Page 77
... The USC doesn’t use the other three bits of the TxSubMode field in Isochronous mode, nor any of the RxSubMode bits, but Zilog reserves these bits for functional extensions in future products. Software should always program them with zeroes in Isochronous mode on a USC. ...
Page 78
... Nine-Bit mode. For example, you probably wouldn’t want to store a Receive Status Block for an address character. The USC doesn’t use the MSBit of the RxSubMode field (CMR7) in Nine Bit mode, but Zilog reserves this bit for future enhancements, and software should program this mode. UM009402-0201 ® ...
Page 79
... Receiver check a CRC code as described in the 'Cyclic Redundancy Checking' section. The USC doesn’t use the RxSubMode field (CMR7-4) in External Sync mode, but Zilog reserves this field for future enhancements and software should program it as 0000 in this mode. ...
Page 80
... The USC doesn’t use the two MSBits of the RxSubMode field (CMR7-5) in Monosync and Bisync modes, nor CMR14 in the TxSubMode field in Monosync mode. Zilog reserves these bits for future enhancements, and software should always program these bits with zeroes in these modes. ...
Page 81
... RSB feature allows in modes like HDLC/SDLC anyway. The USC doesn’t use the three MSBits of the RxSubMode field (CMR7-5) in Transparent Bisync mode, but Zilog reserves these bits for future enhancements and software should always program them as 000 in this mode. ...
Page 82
... X.21. The USC doesn’t use CMR14 in the TxSubMode field in Slaved Monosync mode, but Zilog reserves this bit for future enhancements and software should always pro- gram it as zero in this mode. UM009402-0201 ® ...
Page 83
Z ILOG 5.13 IEEE 802.3 (ETHERNET) MODE Software can select this mode for the Transmitter and the Receiver, by programming 1001 into the TxMode and RxMode fields of the Channel Mode Register (CMR11-8 and CMR3-0). The USC’s capabilities for handling ...
Page 84
... The USC doesn’t use the three LSBits of the TxSubMode field (CMR14-12) in 802.3 mode, nor the three MSBits of RxSubMode (CMR7-5), but Zilog reserves these bits for future enhancements. Software should always program them with zeroes in this mode. ...
Page 85
Z ILOG 5.14 HDLC/SDLC MODE Software can select this mode for both the Transmitter and the Receiver, by writing 0110 to the TxMode and RxMode in the Channel Mode Register (CMR11-8 and CMR3-0). In some sense this is the most ...
Page 86
Z ILOG CMR7-4 Address/Control Processing xx00 The Receiver doesn’t handle the Address or Control field. It simply divides all the data in all received frames into characters per RxLength and places it in the RxFIFO. xx01 The Receiver checks the ...
Page 87
Z ILOG 5.14.2 Frame Length Residuals The Receiver detects and strips inserted zeroes, Flags, and Aborts before any other processing, and doesn’t include these bits/sequences in the RxFIFO nor in CRC calculations. If the Receiver has assembled a partial character ...
Page 88
... CMR13 to 0. The Transmitter sends its accumulated CRC followed by Flags on an Underrun, until another frame is ready to transmit or until software clears CMR13 to 0. Zilog doesn’t recommend this option either, because the frame format probably hasn’t been met when there’s an underrun. ...
Page 89
... RxD onto TxD. CMR12 controls whether the Transmitter sends idle Flags with shared zero bits, as described for normal HDLC/ SDLC mode. Zilog reserves the value 11 in TxCRCType or RxCRCType for future product enhancements; it should not be pro- grammed. The TxCRCStart and RxCRCStart bits (TMR10 and RMR10) control the starting value of the Transmit and Receive CRC generators for each frame or message ...
Page 90
Z ILOG If the TxCRCatEnd bit (TMR8 and the TxMode field (CMR11-8) specifies a synchronous mode, the Transmitter sends the contents of its CRC generator after sending a character marked as EOF/EOM. If TxCRCatEnd is 0 the Transmitter ...
Page 91
Z ILOG 5.16 CYCLIC REDUNDANCY CHECKING (Continued) Used in HDLC/SDLC and 802.3 Modes RxD 5-24 RxFIFO Data (RxLength)-bit Shift Register (RxLength)-bit SI Shift Register M Rx CRC U SI Generator X Used in all other Sync modes ...
Page 92
Z ILOG 5.17 PARITY CHECKING A USC channel can handle a Parity bit in each character in either asynchronous or synchronous modes, although many synchronous protocols use CRC checking only. If the TxParEnab bit in the Transmit Mode Register (TMR5) ...
Page 93
Z ILOG 5.18 STATUS REPORTING The most important status reported by the Transmitter and Receiver is available in the LSBytes of the Transmit and Receive Command/Status Registers (TCSR and RCSR). Figures 5-11 and 5-12 show the format of these registers. ...
Page 94
Z ILOG Start for RxBound, Abort/PE, or RxOver: What's the 1 corresponding IA bit in the RICR? 0 Start for ShortFrame/ CVType or CRCE/FE: Did the last read from the RDR have RxBound=1? No None (The bit is not defined!) ...
Page 95
Z ILOG 5.18 STATUS REPORTING (Continued) Under TCmd Wait Figure 5-11. The Transmit Command/Status Register (TCSR) 5.18.1 Detailed Status in the TCSR PreSent: The Transmitter sets this bit (TCSR7 syn- chronous mode, when ...
Page 96
Z ILOG RCmd(WO) 2ndBE 1stBE Figure 5-12. The Receive Command/Status Register (RCSR) 5.18.2 Detailed Status in the RCSR 2ndBE: The USC sets this read-only bit (RCSR15 when software or an external Receive DMA ...
Page 97
Z ILOG 5.18 STATUS REPORTING (Continued) This bit is not associated with a particular point in the received data stream, for either the Break or Abort condi- tion. (But see the description of “Abort/PE” below for an Abort indication that ...
Page 98
Z ILOG RxOver: The Receiver queues this bit through the RxFIFO with each received character. It sets the bit to indicate a Receive FIFO overrun, but the overrun isn’t visible to software until the character that caused it is the ...
Page 99
... D7-0 (e.g., a system based on an Intel processor) this isn’t a problem. On the other hand, in systems in which even-addressed bytes reside on D15-8 (e.g., a system based on the Zilog Z8000 or 16C0x or a Motorola 680x0) it can cause problems. In such systems, if the last character of a frame falls at an even ...
Page 100
Z ILOG D15-D0 (See Text Write TDR Figure 5-13. A Model of the Transmit Character Counter Feature UM97USC0100 TCLR Non-Zero Detect Counter (TCCR) 0001 Detect UM009402-0201 Z16C30 USC U SER (From Enable TCC Command- Driven Logic) LD EOF/ ...
Page 101
Z ILOG 5.19.1 The Character Counters (Continued) D15-D0 (See Text) LD Counter ON Rx Char Clk LD RCC FIFO RCCR Figure 5-14. A Model of the Receive Character Counter Feature 5-34 RCLR Non-Zero Detect Enable TCC 0000 Detect To Interrupt ...
Page 102
Z ILOG On the Receive side, software can’t directly read the RCC (except perhaps by using test modes that are beyond the scope of this section). Instead, when the Receiver detects an end-of-frame situation, it captures the decremented value in ...
Page 103
... Register (CCSR4-2) without affecting the rest of the CCSR. The channel ignores bits 11-5 and 1-0 of the first or only word, but Zilog reserves these bits for future enhance- ments and software should ensure that they’re all zero. A channel transfers the second word of a 32-bit TCB through the Transmit Count Limit Register (TCLR) and into the TC Counter (TCCR) ...
Page 104
Z ILOG RCCF RCCF Clear DPLL DPLL Ovflo Avail RCCF Sync 2Miss Figure 5-15. The Channel Command/Status Register (CCSR) Wait4 Flag Tx Pre TxCtrlBlk Sync:TxPreL Trig Amble Figure 5-16. The ...
Page 105
Z ILOG 5.19.4 Receive Status Blocks A USC Receiver sets the RxBound bit in the RxFIFO to indicate the end of a frame, message, or word, in External Sync, Transparent Bisync, 802.3, and HDLC/SDLC. In these modes the Receiver can ...
Page 106
Z ILOG The only trouble with the 32-bit RSB option is that software has to know how long each received frame is, in order to find the RSB that indicates the length. (This is somewhat similar to trying to follow ...
Page 107
... Writing all zeroes to any of the command fields does nothing, which can be useful when the intent is to write to other fields of the register. Zilog reserves other values not listed below for future extensions to the USC family; such values should not be written to the subject field. ...
Page 108
Z ILOG RTCmd Figure 5-19. The Channel Command/Address Register (CCAR) A description of each command follows, in alphabetical order. Some of them include references to other chapters or sections, which provide more information that’s impor- ...
Page 109
... Zilog Z8000, Zilog 16C0x and Motorola 680x0 processors. “D7-0 First” should be programmed for the Zilog Z380 and most Intel processors. A channel applies this option only during a 16-bit transfer, between the TxFIFO or RxFIFO and the AD15-0 pins. However, if the ...
Page 110
Z ILOG Select RICRHi=/INT Level (RCmd:=0110): this command conditions a channel so that subsequent accesses to the MSByte of its Receive Interrupt Control Register (RICR15- 8) read or write the number of received characters at which the channel starts requesting ...
Page 111
Z ILOG 5.20 COMMANDS (Continued) Trigger Channel Load DMA (RTCmd:=00100): Chapter 7 will describe how this command puts a channel in a special mode in which an external Transmit DMA controller can initialize all the registers in the channel. Software ...
Page 112
... On a Zilog Z8000 or 16C0x or Motorola 680x0 based system this means that software should write bytes to the TDR and read bytes from the RDR at an odd address Zilog Z380 ™ or Intel 80x86 processor, software should write bytes to the TDR and read bytes from the RDR at an even address ...
Page 113
Z ILOG 5.22.3 Fill Levels Each channel maintains a counter for each FIFO that reflects its current contents. Software can read the number of received characters/bytes that are currently in the RxFIFO this, it may first have to ...
Page 114
Z ILOG 5.23 HANDLING OVERRUNS AND UNDERRUNS In general, both the Tx Underrun condition in the TCSR and the Rx Overrun condition in the RCSR should be enabled and armed for interrupt. While the USC can handle most things that ...
Page 115
Z ILOG 5.23 HANDLING OVERRUNS AND UNDERRUNS (Continued USC manufactured after June of 1993, write a “Purge Rx” command to the CCAR earlier device, write a “Purge Rx FIFO” command to the CCAR and write ...
Page 116
Z ILOG 5.24 BETWEEN FRAMES, MESSAGES, OR CHARACTERS 5.24.1 Synchronous Transmission When software issues a “Set EOF/EOM” command and then writes data to a channel’s TDR, or when the TCC is enabled and software or an external Transmit DMA con- ...
Page 117
Z ILOG 5.24 BETWEEN FRAMES, MESSAGES, OR CHARACTERS (Continued) In sync modes, once the conditions to start sending a message or frame (described above) are met, the Trans- mitter may send a bit sequence called a Preamble. A Preamble can ...
Page 118
Z ILOG 5.24.3 Synchronous Reception Between the end of one message or frame and the start of the next, the Receiver goes through states that are similar to the inter-message or inter-frame activities that are de- scribed above for the ...
Page 119
... Z ILOG © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc ...
Page 120
Z ILOG 6.1 INTRODUCTION Chapter 5 described many of the features of the USC support handling serial traffic via DMA, that is, without processor intervention on a byte-by-byte basis. This chap- ter describes how to interface external DMA controllers and ...
Page 121
Z ILOG 6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION (Continued) DMAC data Memory Address Memory Location /RD Data /WR DMA Request (e.g., /TxREQ) Figure 6-1. Flowthrough DMA Transfer, Memory to Peripheral Device 6-2 REQ Device Memory from Memory to DMAC UM009402-0201 ...
Page 122
Z ILOG DMAC Memory Address Data Register in Device /RD Data /WR DMA Request (e.g., /RxREQ) Figure 6-2. Flowthrough DMA Transfer, Peripheral Device to Memory UM97USC0100 REQ data data Device Memory from Device to DMAC If the device doesn't have ...
Page 123
Z ILOG 6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION (Continued) Address /RD Data /WR DMA Request (e.g., /TxREQ) DMA Acknowledge (e.g., /TxACK) Figure 6-3. Flyby DMA Transfer, Memory to Peripheral Device 6-4 ACK DMAC REQ data Memory Device Memory Location from ...
Page 124
Z ILOG Address /RD Data /WR DMA Request (e.g., /RxREQ) DMA Acknowledge (e.g., /RxACK) Figure 6-4. *Flyby DMA Transfer, Peripheral Device to Memory UM97USC0100 ACK DMAC REQ data Memory Device Memory Location from Device to Memory If the device doesn't ...
Page 125
Z ILOG 6.2 FLYBY VS. FLOWTHROUGH DMA OPERATION (Continued) Figures 6-3 and 6-4 illustrate flyby (single-cycle) opera- tion. In addition to the Request signal from the device to the DMA controller, there’s an Acknowledge signal from the DMAC back to ...
Page 126
Z ILOG “Forcing out a frame” in D1. above applies only in HDLC/ SDLC, HDLC/SDLC Loop, 802.3, or Transparent Bisync, and operates differently on USCs manufactured before or after June 1993. On the older devices, the Receiver set a state ...
Page 127
Z ILOG 6.3.1 Programming the DMA Request Levels (Continued) Code that writes or reads a DMA Request threshold must ensure that no interrupts will occur between the time it writes the “Select xICRHi=REQ Level” command to the TCSR or RCSR, ...
Page 128
... Z ILOG © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc ...
Page 129
... These capabilities can be used to their best advantage in a system including a Zilog processor and other Zilog peripherals, but it’s easy to interface the USC to interrupt other processors as well. This chapter describes the USC’s interrupt capabilities and how to use them in various system applications ...
Page 130
Z ILOG 7.2 INTERRUPT ACKNOWLEDGE DAISY-CHAINS (Continued) Host MPU /IACK /IRQ VCC IEI Peripheral A 7.3 EXTERNAL INTERRUPT CONTROL LOGIC There are two valid reasons why a system designer might choose not to use an interrupt acknowledge daisy chain (plus ...
Page 131
Z ILOG /INT, /INTB IUSC 7.4 USING /RXREQ AND /TXREQ AS INTERRUPT REQUESTS When an external DMA controller isn’t used to handle the Receive or Transmit data for a channel, the corresponding REQ pin isn’t used to output a DMA ...
Page 132
Z ILOG 7.5 INTERRUPT TYPES AND SOURCES Internally, the USC uses a daisy-chaining scheme much like that described earlier. Each channel includes six interrupt “types”, that are arranged in a fixed priority order. Four of the six types include several ...
Page 133
Z ILOG Sources Exited Hunt IA Idle Received IA Break/Abort IA Rx Boundary IA Abort/Parity Error IA Rx Overrun IA Preamble Sent IA Idle Set IA Abort Sent IA EOF/EOM Sent IA CRC Sent IA Tx Underrun IA /RxC Fall ...
Page 134
... Each individual source has an associated register bit that we’ll call its Interrupt Arm or IA bit. (Previous Zilog docu- ments called this bit an Interrupt Enable or IE bit, but also used the same term for another bit that applies to the entire type ...
Page 135
Z ILOG tIE ADnb D Q WRREGb /Q CLR Reset Source "s" sIA ADna D Q From Other Sources WRREGa /Q CLR Reset /IACKcy DLC NV Iack Read Figure 7-4. A Model of the Interrupt Logic for Source “s” and ...
Page 136
Z ILOG 7.7 DETAILS OF THE MODEL The IA and IE bits appear near the left side of Figure 7-4, as D-type flip-flops that capture the state line when software writes a specific register. The IP bit ...
Page 137
Z ILOG 7.8 INTERRUPT OPTION IN THE BCR One bit in the Bus Configuration Register (BCR) affects the interrupt subsystem. This information is also presented in Chapter 2, Bus Interfacing. 2PulseIACK (Double-Pulse Interrupt Acknowledge; BCR1): software should program this bit ...
Page 138
Z ILOG 7.9 INTERRUPT ACKNOWLEDGE CYCLES (Continued) AD15-AD0 /SITACK /AS IEO IEI /DS OR /RD /WAIT//RDY (as Wait) /WAIT//RDY (as Ack) /INT Figure 7-5. An Interrupt Acknowledge Cycle signalled by /SITACK Multiplexed Bus 7-10 (not used) vector UM009402-0201 ...
Page 139
Z ILOG Figure 7-6 shows an interrupt acknowledge cycle that’s signalled by /SITACK bus with separate address and data lines. (As before there are two subcases of this kind of cycle, depending on whether the host processor uses ...
Page 140
Z ILOG 7.9 INTERRUPT ACKNOWLEDGE CYCLES (Continued) Figure 7-7 shows the kind of interrupt acknowledge cycle that the USC expects when /PITACK goes low and the 2PulseIACK bit (BCR1 Here a single pulse on /PITACK substitutes for the ...
Page 141
Z ILOG Figure 7-8 shows the kind of interrupt acknowledge cycle that the USC expects when /PITACK goes low and the 2PulseIACK bit (BCR1 Here, two consecutive low pulses on /PITACK constitute the complete interrupt ac- knowledge cycle, ...
Page 142
Z ILOG 7.10 INTERRUPT ACKNOWLEDGE VS. READ CYCLES Interrupt Acknowledge cycles are similar to the cycles that occur when the host processor reads a USC register, which are discussed in Chapter 2. However, the user should note the following ways ...
Page 143
Z ILOG If the IA bit for this source is 1, the interrupt Abort/PE logic sets the RS IP bit when software or the Receive DMA channel reads a char- acter from the RxFIFO that failed parity checking, or, in ...
Page 144
Z ILOG 7.11.2 Receive Data Interrupts (Continued) To program the Receive Data Interrupt Request Level, first write the “Select RICRHi=/INT Level” command to the RCmd field of the Receive Command/Status Register (RCSR15-12). Then write the number of received charac- ters ...
Page 145
Z ILOG Start: Interrupt with Vector = "Rx Data" IF NECESSARY, write 0101 to RCmd (RCSR15-12) Read FIFO count CT: = RICR15-8 CT=0? No Read Status from RCSR. Handle bits other than RxBound as required. End of Frame? RxBound (RCSR4) ...
Page 146
Z ILOG 7.11.2 Receive Data Interrupts (Continued) TCmd Rsrvd Figure 7-12. The Transmit Command/Status Register (TCSR) "TxFIFOStatus" if last TCSR 15-12 command 4-7 was 5 "Tx Int level" if last RCSR 15-12 command 4-7 was ...
Page 147
Z ILOG the corresponding bit in the Transmit Command/Status Register (TCSR) goes from bit is 0, the corresponding TCSR bit has no effect on the IP bit and thus will not cause interrupts. The ...
Page 148
Z ILOG 7.11.5 I/O Pin Interrupt Sources and IA Bits The interrupt logic can set the I/O Pin IP bit in response to rising and/or falling edges on any of six pins for each channel, namely /RxC, /TxC, /RxREQ, /TxREQ, ...
Page 149
Z ILOG 7.12 INTERRUPT PENDING AND UNDER SERVICE BITS Software can read, set, and clear the Interrupt Pending (IP) and Interrupt Under Service (IUS) bits, for all six interrupt types in a USC channel, via the Daisy-Chain Control Register (DCCR). ...
Page 150
Z ILOG 7.13 INTERRUPT ENABLE BITS Software can read, set, and clear the Interrupt Enable (IE) bits for all six interrupt types in a USC channel, in the LSByte of its Interrupt Control Register (ICR). Figure 7-17 shows the ICR. ...
Page 151
Z ILOG The Vector Includes Status field (VIS; ICR12-9) controls whether the vector, that the channel returns during an interrupt acknowledge cycle in which the highest-priority requesting type is in the channel, identifies the type or not. Such vector modification ...
Page 152
Z ILOG 7.15 INTERRUPT VECTORS (Continued) Interrupt Vector 7-4 (RO Figure 7-18. The Interrupt Vector Register (IVR) 7.16 SOFTWARE REQUIREMENTS This chapter having described the features and functions of the USC that relate to interrupts, ...
Page 153
Z ILOG 7.16.3 Handling a Type The process of handling a single type of interrupt is the same regardless of whether the overall ISR handles only the highest priority pending type, or all the pending types within the device. The ...
Page 154
Z ILOG 7.16.3 Handling a Type (Continued) Transmit Data Type 1. Write the DCCR to clear the IP bit 2a. Write the TDR often enough to bring the number of empty bytes in the TxFIFO below the “Tx Data Interrupt ...
Page 155
... Transmitter finishes the frame, typically by sending the CRC and closing Flag. © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice ...
Page 156
Z ILOG 8.1 INTRODUCTION This chapter includes a bit by bit description of all the registers in the IUSC. 8.2 ABOUT RESETTING The USC is placed in an initial inactive state whenever external hardware drives the /RESET pin low. In ...
Page 157
... Zilog’s SCC family. Still, initializing registers in the wrong order can thoroughly confuse the USC’s internal logic and make it do strange things. Always initialize the USC in the following order: 1. Set the pin configurations in the IOCR. While it’ ...
Page 158
... Z ILOG 8.5 DETERMINING THE DEVICE REVISION LEVEL Zilog makes every effort to improve devices like the 16C30 while preserving compatibility with software developed on earlier devices. Nonetheless, for some purposes (like using new features) software needs to tell which revision of the device it’s operating on, and behave differently for different revisions ...
Page 159
Z ILOG 8.6.2 COMMON SOFTWARE PROBLEMS (Continued) S2. WordStatus problems In general, software wants to program the WordStatus bit (RICR3) the same as BCR2, which indicates whether your application uses a 16-bit bus. If software or the Rx DMA channel ...
Page 160
Z ILOG S7. Interrupt handling A new section at the end of Chapter 7 gives specific requirements for each type of interrupt. In general, the strategy is 1) clear IP, 2) read the status bits, handle them including clearing/unlatching them, ...
Page 161
... Z ILOG 8.7 TEST MODES The USC includes a facility intended for Zilog’s device testing, that gives software access to certain internal signals and registers that are not otherwise accessible. The low-order bits of the Test Mode Control Register TMCR4-0 Signals/Register Selection 00001 TMDR15-8: Rx shift register, MSbyte ...
Page 162
Z ILOG D15 D14 D13 D12 D11 D10 Figure 8-1. Test Mode Data Register with TMCR 4-0=00101 (Clock Mux Outputs) UM97USC0100 UM009402-0201 Z16C30 USC SER ...
Page 163
Z ILOG 8.7 TEST MODES (Continued) D15 D14 D13 D12 D11 D10 Figure 8-2. Test Mode Data Register with TMCR 4-0=00111 (Clock Mux Inputs) 8 UM009402-0201 Z16C30 USC U SER D0 ...
Page 164
Z ILOG D15 D14 D13 D12 D11 D10 Figure 8-3. Test Mode Data Register with TMCR 4-0=01110 (I/O and Misc Status) UM97USC0100 UM009402-0201 Z16C30 USC SER S D0 ...
Page 165
Z ILOG 8.8 REGISTER REFERENCE The following pages include all of the fields in all of the registers in one of the USC’s channels, plus the Bus Configuration Register which is common to both channels. They are arranged in alphabetical ...
Page 166
Z ILOG Bus Configuration Register (BCR) SepAd Field/Bit Conditions Bit(s) Name /Context 8-bit bus BCR15 SepAd 16-bit bus BCR2 16-Bit /PITACK BCR1 2PulseIACK used BCR0 SRightA Muxed Read/Write Read Only, ...
Page 167
Z ILOG Channel Command/Address Register (CCAR) RTCmd Field/Bit Conditions Bit(s) Name /Context CCAR15-12 RTCmd CCAR10 RTReset CCAR9-8 RTMode CCAR7 ChanLoad Channel Load DMA CCAR6 B//W 16-bit bus CCAR5-1 RegAddr CCAR0 U// Read/Write, RO ...
Page 168
Z ILOG Channel Command/Status Register (CCSR) RCCF RCCF Clear DPLL DPLL RCCF Ovflo Avail Sync 2Miss Field/Bit Conditions Bit(s) Name /Context CCSR15 RCCF Ovflo RCC Enabled CCSR14 RCCF Avail CCSR13 Clear RCCF CCSR12 DPLL Sync ...
Page 169
Z ILOG Channel Control Register (CCR) Flag Wait4 Pre TxCtrlBlk Tx Trig Sync:TxPreL Amble Field/Bit Conditions Bit(s) Name /Context CCR15-14 TxCtrlBlk CCR13 Wait4TxTrig Sync Flag H/SDLC, CCR12 Preamble CCR9-8 =01 CCR11-8 TxShaveL Async, CMR15=1 CCR11-10 ...
Page 170
Z ILOG Channel Mode Register (CMR) TxSubMode Because the content of the SubMode fields depends on the Mode fields, the following descriptions are grouped by mode. TxSubMode and RxSubMode bits that are not shown for ...
Page 171
Z ILOG Channel Mode Register (CMR) (Continued) Because the content of the SubMode fields depends on the Mode fields, the following descriptions are grouped by mode. TxSubMode and RxSubMode bits that are not shown for a particular Mode value are ...
Page 172
Z ILOG Channel Mode Register (CMR) (Continued) Because the content of the SubMode fields depends on the Mode fields, the following descriptions are grouped by mode. TxSubMode and RxSubMode bits that are not shown for a particular Mode value are ...
Page 173
Z ILOG Clock Mode Control Register (CMCR) CTR1Src CTR0Src BRG1Src Field/Bit Conditions Bit(s) Name /Context CMCR15-14 CTR1Src CMCR13-12 CTR0Src CMCR11-10 BRG1Src CMCR9-8 BRG0Src CMCR7-6 DPLLSrc CMCR5-3 TxCLKSrc CMCR2-0 RxCLKSrc RW = Read/Write Read ...
Page 174
Z ILOG Daisy Chain Control Register (DCCR) IUS (WO) IUS IUS IUS Field/Bit Conditions Bit(s) Name /Context DCCR15-14 IUS Op Write DCCR13 RS IUS Read Write DCCR12 RD IUS Read Write ...
Page 175
Z ILOG Hardware Configuration Register (HCR) CTR1 CTR0Div CVOK DPLLDiv DSel Field/Bit Conditions Bit(s) Name /Context HCR15-14 CTR0Div HCR13 CTR1DSel HCR12 CVOK Biphase HCR11-10 DPLLDiv HCR9-8 DPLLMode HCR7-6 TxAMode HCR5 BRG1S HCR4 BRG1E RxAMode HCR3-2 ...
Page 176
Z ILOG Input/Output Control Register (IOCR) CTSMode DCDMode TxRMode Field/Bit Conditions Bit(s) Name /Context IOCR15-14 CTSMode IOCR13-12 DCDMode IOCR11-10 TxRMode IOCR9-8 RxRMode IOCR7-6 TxDMode IOCR5-3 TxCMode IOCR2-0 RxCMode RW = Read/Write Read Only, ...
Page 177
Z ILOG Interrupt Control Register (ICR) MIE DLC Field/Bit Conditions Bit(s) Name /Context ICR15 MIE ICR14 DLC ICR13 NV ICR12-9 VIS ICR7 Write ICR5 RS IE Read Write ICR4 RD IE Read ...
Page 178
Z ILOG Interrupt Vector Register (IVR) Interrupt Vector7-4 (RO) Type Code (RO Field/Bit Conditions Bit(s) Name /Context IVR15-12 Read IVR15-8, TypeCode IVR11-9 or IAck w/ highest pending type enabled by ICR12-9 IVR8 IVR7-0 Read/Write IVR7-0, ...
Page 179
Z ILOG Miscellaneous Interrupt Status Register (MISR) RxCL/U /RxC TxCL/U /TxC RxRL/U /RxR TxRL Field/Bit Conditions Bit(s) Name /Context MISR15 RxCL/U Read Write MISR14 /RxC RxCL/U=1 RxCL/U=0 MISR13 TxCL/U Read Write MISR12 /TxC TxCL/U=1 TxCL/U=0 ...
Page 180
Z ILOG Receive Character Count Register (RCCR Field/Bit Conditions Bit(s) Name /Context RCCAvail RCCR15-0 (CCSR14 Read/Write Read Only Write Only – for other codes see p. 8-10. UM97USC0100 ...
Page 181
Z ILOG Receive Command/Status Register (RCSR) Rcmd (WO) RxResidue 2ndBE 1stBE Field/Bit Conditions Bit(s) Name /Context RCSR15-12 RCmd Sync 0000=no operation; 0001=Reserved; 0010=Clear Receive CRC Generator; 0011=Enter Hunt Mode; 0100=Reserved; 0101=Select RICRHi=RxFIFO Status; 0110=Select RICRHi=/INT ...
Page 182
Z ILOG Receive Count Limit Register (RCLR Field/Bit Conditions Bit(s) Name /Context RCLR15-0 Receive Data Register (RDR) Received character: read only using 16-bit operation Field/Bit Conditions Bit(s) Name /Context RDR15-8 ...
Page 183
Z ILOG Receive Interrupt Control Register (RICR) "RxFIFO Status" if last RCSR15-12 command 4-7 was 5 "Rx Int level" if last RCSR15-12 command 4-7 was 6 "RxREQ level" if last RCSR15-12 command 4-7 was ...
Page 184
Z ILOG Receive Mode Register (RMR) RxDecode RxCRCType Field/Bit Conditions Bit(s) Name /Context RMR15-13 RxDecode RMR12-11 RxCRCType Sync RMR10 RxCRCStart Sync RMR9 RxCRCEnab Sync RMR8 QAbort HDLC/ SDLC RMR7-6 RxParType RMR5 RxParEnab RMR4-2 RxLength RMR1-0 ...
Page 185
Z ILOG Status Interrupt Control Register (SICR) RxCDn RxCUp TxCDn TxCUp RxRDn Field/Bit Conditions Bit(s) Name /Context SICR15 RxCDn IA SICR14 RxCUp IA SICR13 TxCDn IA SICR12 TxCUp IA SICR11 ...
Page 186
Z ILOG Test Mode Data Register (TMDR Field/Bit Conditions Bit(s) Name /Context TMDR15-0 Test Constant 0 Register (TC0R Field/Bit Conditions Bit(s) Name /Context TC0R15-0 Write, or Read w/ TC0RSel (RICR0)=0 ...
Page 187
Z ILOG Transmit Character Count Register (TCCR Field/Bit Conditions Bit(s) Name /Context TCCR15 Read/Write Read Only Write Only – for other codes see p. 8-10. 8-32 Current value of ...
Page 188
Z ILOG Transmit Command/Status Register (TCSR) Under TCmd Wait Field/Bit Conditions Bit(s) Name /Context TCSR15-12 TCmd Sync TICR2=1 H/SDLC T.Bisync Sync TCSR11 Sync UnderWait TCSR10-8 TxIdle TCSR7 PreSent Sync TCSR6 IdleSent TCSR5 AbortSent H/SDLC TCSR4 ...
Page 189
Z ILOG Transmit Data Register (TDR) Transmit character: write only using 16-bit operation Field/Bit Conditions Bit(s) Name /Context TDR15-8 16-bit bus TDR7 Read/Write Read Only Write Only – for ...
Page 190
Z ILOG Transmit Interrupt Control Register (TICR) "TxFIFO Status" if last TCSR15-12 command 4-7 was 5 "Tx/Int level" if last TCSR15-12 command 4-7 was 6 "TxREQ level" if last TCSR15-12 command 4-7 was Field/Bit ...
Page 191
Z ILOG Transmit Mode Register (TMR) TxEncode TxCRCType Field/Bit Conditions Bit(s) Name /Context TMR15-13 TxEncode TMR12-11 TxCRCType Sync TMR10 TxCRCStart Sync TMR9 TxCRCEnab Sync TMR8 TxCRCat Sync End TMR7-6 TxParType TMR5 TxParEnab TMR4-2 TxLength TMR1-0 ...
Page 192
... Z ILOG © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc ...
Page 193
Z ILOG A.1 INTRODUCTION This is for the reader of previous USC documentation. It summarizes the changes in the names of registers and commands that were made in this document, with a few words about why they were changed. A.1.1 ...
Page 194
... Tx DMA channel or software loads new Tx data after a Tx Underrun has occurred (p 5-50). © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice ...
Page 195
... No Q: What technology is used to make the USC and IUSC? A: The USC family is fabricated in an N-well CMOS technology. The USC and IUSC are currently in 1.6 Included micron, with the IUSC moving to Zilog’s 0.8 micron technology in 1994. ™ technical Z16C30 USC U ...
Page 196
... Q: What products does the Electronic Programmer’s Manual (EPM A: There are EPMs available for the USC and IUSC. They can be purchased from the local Zilog Sales Office or Zilog distributor. Q: Should the unused pins of the (I)USC be tied High, Low, or left floating (i.e., /TxREQ, /CTS, /DCD,...)? A: The basic rules are: Unused OUTPUT ONLY pins can be left unterminated ...
Page 197
... Ethernet on a backplane if minimum node distances are violated? A: This question applies to the layer 1 device driver used and is out of the scope of the Zilog USC family specification. it sees is the one to synchronize to; if this is not the case the DPLL will have to see “n” correct edges before it will be in sync. This “ ...
Page 198
Z ILOG SERIAL & PROTOCOL QUESTIONS AND ANSWERS (Continued) Q: Running asynchronous mode, how do you program a USC family device to achieve a certain baud rate with a predetermined external clock? That is, do you need to use the ...
Page 199
... Thus they are one’s in the normal case and zero’s in the case of a framing error USC family devices have a Recovery Time like the Zilog Z8530 SCC does? A: No. The USC family does not have a recovery time. The Bus Cycle Time (AC Spec #1) specifies the access time of the device ...
Page 200
... Q: Is the rated serial data rate aggregate the rated speed for each receiver/transmitter? A: Zilog specifies the maximum rated serial data rate for each receiver/transmitter independently (not aggre- gate). Q: What is the maximum clock frequency for the Port 0 & ...