DS2482S-800+T&R Maxim Integrated Products, DS2482S-800+T&R Datasheet - Page 4

• Manufacturer Part Number: DS2482S-800+T&R
• Description: IC MASTER I2C-1WIRE 8CH 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS2482S-800+T&R

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 3.3 V, 5V
• Current - Supply: 750µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
PIN DESCRIPTION
PIN
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
NAME
Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at
400KHz in Overdrive.
With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the
passive pullup on threshold V
capacitive load on the 1-Wire bus must not exceed 300pF.
Active pullup guaranteed to turn on between V
Active or resistive pullup choice is configurable.
Fall time high to low (t
These values apply at full load, i. e., 1nF at standard speed and 0.3nF at Overdrive speed. For
reduced load, the pulldown slew rate is slightly faster.
All I²C timing values are referred to V
Applies to SDA, SCL, and AD0, AD1, AD2.
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V
signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
SCL signal.
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
t
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t
standard-mode I²C-bus specification) before the SCL line is released.
C
to I²C-Bus Specification v2.1 are allowed.
I²C communication should not take place for the max t
Except for t
Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of
these parameters deviate from their typical value in the same direction and by the same degree.
SU
GND
SDA
SCL
AD2
AD1
AD0
IO3
V
IO7
IO6
IO5
IO4
IO0
IO1
IO2
NC
B
:
CC
DAT
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
 2 50ns must then be met. This is automatically the case if the device does not stretch the LOW
F1
IO Driver for 1-Wire Line #3
I²C Serial Clock Input; must be tied to V
I²C Serial Data Input/Output; must be tied to V
Power Supply Input
Not Connected
I²C Address Inputs; must be tied to V
address of the device, see Figure 8.
IO Driver for 1-Wire Line #7
IO Driver for 1-Wire Line #6
IO Driver for 1-Wire Line #5
IO Driver for 1-Wire Line #4
Ground Reference
IO Driver for 1-Wire Line #0
IO Driver for 1-Wire Line #1
IO Driver for 1-Wire Line #2
, all 1-Wire timing specifications and t
HD
:
DAT
F1
has only to be met if the device does not stretch the LOW period (t
) is derived from PD
IL1
may not be reached in the available time. With Overdrive speed the
IHmin
and V
4 of 23
SRC,
IL1MAX
ILmax
referenced from 0.9 × V
CC
SU
APUOT
FUNCTION
:
DAT
CC
or GND. These inputs determine the I²C slave
levels.
and V
OSCWUP
through a pullup resistor.
= 1000 + 250 = 1250ns (according to the
are derived from the same timing circuit.
CC
IH1MIN
through a pullup resistor.
time following a power-on reset.
.
CC
is switched off.
CC
to 0.1 × V
CC
.
IHmin
LOW
) of the
of the SCL