DS2143Q/T&R Maxim Integrated Products, DS2143Q/T&R Datasheet - Page 13

IC CONTROLLER E1 5V LP 44-PLCC

DS2143Q/T&R

Manufacturer Part Number
DS2143Q/T&R
Description
IC CONTROLLER E1 5V LP 44-PLCC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS2143Q/T&R

Controller Type
E1 Controller
Interface
Parallel/Serial
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS2143Q/T&RDS2143Q/T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
CCR: COMMON CONTROL REGISTER (Address=14 Hex)
LOCAL LOOPBACK
When CCR.7 is set to a 1, the DS2143 will enter a Local LoopBack (LLB) mode. This loopback is useful
in testing and debugging applications. In LLB, the DS2143 will loop data from the transmit side back to
the receive side. This loopback is synonymous with replacing the RCLK input with the TCLK signal, and
the RPOS/RNEG inputs with the TPOS/TNEG outputs. When LLB is enabled, the following will occur:
1. data at RPOS and RNEG will be ignored;
2. all receive side signals will take on timing synchronous with TCLK instead of RCLK;
3. all functions are available.
(MSB)
LLB
SYMBOL
RHDB3
THDB3
RCRC4
TCRC4
TG802
RG802
RSM
LLB
THDB3
POSITION
CCR.7
CCR.6
CCR.5
CCR.4
CCR.3
CCR.2
CCR.1
CCR.0
TG802
NAME AND DESCRIPTION
Local Loopback.
0 = loopback disabled.
1 = loopback enabled.
Transmit HDB3 Enable.
0 = HDB3 disabled.
1 = HDB3 enabled.
Transmit G.802 Enable. See Section 13 for details.
0 = do not force TCHBLK high during bit 1 of timeslot 26.
1 = force TCHBLK high during bit 1 of timeslot 26.
Transmit CRC4 Enable.
0 = CRC4 disabled.
1 = CRC4 enabled.
Receive Signaling Mode Select.
0 = CAS signaling mode.
1 = CCS signaling mode.
Receive HDB3 Enable.
0 = HDB3 disabled.
1 = HDB3 enabled.
Receive G.802 Enable. See Section 13 for details.
0 = do not force RCHBLK high during bit 1 of timeslot 26
1 = force RCHBLK high during bit 1 of timeslot 26.
Receive CRC4 Enable.
0 = CRC4 disabled.
1 = CRC4 enabled.
TCRC4
13 of 44
RSM
RHDB3
RG802
DS2143/DS2143Q
RCRC4
(LSB)

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