DS21Q43-ATN Maxim Integrated Products, DS21Q43-ATN Datasheet - Page 10

• Manufacturer Part Number: DS21Q43-ATN
• Description: IC FRAMER E1 QUAD 5V 128-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q43-ATN

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 32mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS21Q43A
Receive Channel Clock [RCHCLK]. 256 kHz clock which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data. See
Section 11 for timing details.
Receive Channel Block [RCHBLK]. A user programmable output that can be forced high or low during
any of the 32 E1 channels. Synchronous with RCLK when the transmit side elastic store is disabled.
Synchronous with RSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks
to a serial UART or LAPD controller in applications where not all E1 channels are used such as
Fractional E1, 384 kpbs service (H0), 1920 kpbs (H12), or ISDN-PRI. Also useful for locating individual
channels in drop-and-insert applications and for per-channel loopback. See Section 11 for timing details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either
frame (RCR1.6=0) or multiframe boundaries (RCR1.6=1). If the receive side elastic store is enabled via
RCR2.1, then this pin can be enabled to be an input at which a frame boundary pulse is applied. See
Section 11 for timing details.
Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse, one RCLK wide, is output at this pin which
identifies frame boundaries. See Section 11 for timing details.
Receive Multiframe Sync [RMSYNC]. Only used when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this pin which identifies either CAS or CRC4
multiframe boundaries. If the receive side elastic store is disabled, then this output should be ignored. See
Section 11 for timing details.
Receive Bipolar Data Inputs [RPOS and RNEG]. Sampled on falling edge of RCLK. Tie together to
receive NRZ data and disable bipolar violation monitoring circuitry.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications that do not use the elastic store. Allowing this pin
to float can cause the device to 3-state its outputs.
Receive Loss of Sync/Loss of Transmit Clock [RLOS/LOTC]. A dual function output. If CCR1.6=0,
then this pin will toggle high when the synchronizer is searching for the E1 frame or multiframe. If
TCR2.0=1, then this pin will toggle high the TCLK pin has not been toggled for 5 s.
Receive Alarm Interrupt [
]. Flags host controller during conditions defined in the Status Registers
INT
of the four framers. User can poll the Interrupt Status Register (ISR) to determine which status register in
which framer is active (if any). Active low, open drain output.
3-State Control [TEST]. Set high to 3-state all output and I/O pins (including the parallel control port).
Set low for normal operation. Useful in board-level testing.
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
10 of 60