DS3148 Maxim Integrated Products, DS3148 Datasheet - Page 19

• Manufacturer Part Number: DS3148
• Description: IC 8CH DS3/3 FRAMER 349-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3148

• Controller Type: DS3/E3 Framer
• Interface: LIU
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 640mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 349-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 7-2. Transmit Clock Block Diagram
7.2.2 Loss-of-Clock Detection
The LOTC and LORC (loss-of-receive clock) status bits in the
receive (RCLK) clocks are stopped, respectively. The clocks are monitored with the system clock (SCLK), which
must be running for the loss-of-clock circuits to function properly. The LOTC and LORC status bits are set when
TICLK or RCLK have been stopped high or low for between 9 and 21 clock periods (depending on SCLK
frequency). The LOTC and LORC status bits are cleared after the device detects a few edges of the monitored
clock.
7.3 Receiver Logic
In the normal operating mode, the signals on RPOS and RNEG are decoded as an HDB3 signal in E3 mode or as
a B3ZS signal in DS3 mode and output on the RDAT pin. The input signal is monitored for loss-of-signal, bipolar
violations, excessive zeros, AIS, unframed all ones and, after decoding, is sent to the BERT and synchronizer.
When the synchronizer finds the framing pattern in the overhead bits, it clears the out-of-frame indication (ROOF)
and aligns the start-of-frame (RSOF) and data-enable (RDEN) signals to the signal on RDAT. If the framing pattern
is lost, then ROOF is set and the framing pattern is searched for again. While the framing pattern is being searched
for, the RSOF and RDEN signals maintain the alignment with the last known position of the framing pattern. If a
framing pattern is found in a new position, the RSOF and RDEN signals align with the new pattern position and the
COFAL status bit is set in the
no relationship with any framing pattern until one is found. The signal on the ROOF pin can be monitored using the
OOF bit in the
register, RCLK, RPOS, and RNEG are replaced with TICLK, TPOS, and TNEG. This allows the framer and
synchronizer logic to be checked in order to isolate a problem in the system. The BERT can monitor either the
payload or the entire signal for expected test patterns.
Figure 7-3. Receiver Block Diagram
FROM Tx DLB
TICLK
RCLK
TICLK
RNEG
RPOS
RCLK
T3E3SR
LOTCMC
DLB
LORC
LOTC
register. When the diagnostic loopback mode is enabled using the DLB bit in the
T3E3SRL
PLB
DLB
DECODER
B3ZS
HDB
AMI
register. After reset, the RSOF and RDEN signals are generated, but have
1
0
19 of 89
TDAT
INTERNAL TCLK
SYNCHRONIZER
MSR
E3 G.751
LLB
1
0
DS3
Rx BERT
register are set when the transmit (TICLK) and
FROM Tx BERT
TCLK
TO PLB MUX
RLOS
ROOF
RSOF
RDEN
RDAT
ROCLK
MC2