Z8523016PEC Zilog, Z8523016PEC Datasheet - Page 76

• Manufacturer Part Number: Z8523016PEC
• Description: IC 16MHZ ESCC XTEMP 40-DIP
• Manufacturer: Zilog

Specifications of Z8523016PEC

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3052

PS005308-0609
Z80230 Read Cycle Timing
Z80230 Interrupt Acknowledge Cycle Timing
The Read Cycle Timing for the Z80230 is displayed in
A7-A0, as well as the state of CS0 and INTACK, are latched by the rising edge of AS.
R/W must be High before DS falls to indicate a Read cycle. The Z80230 data bus drivers
are enabled while CS1 is High and DS is Low.
The Interrupt Acknowledge cycle timing for the Z80230 is displayed in
72. The address on A7-A0 and the state of CS0 and INTACK are latched by the rising -
edge of AS. However, if INTACK is Low. The address on A7-A0, CS0, CS1, and R/W
are ignored for the duration of the interrupt acknowledge cycle.
The Z80230 samples the state of INTACK on the rising edge of AS, and AC parameters.
Parameters 7 and 8 of
Between the rising edge of AS and the falling edge of DS, the internal and external daisy
chains settle, as specified in parameter 29. A system with no external daisy chain provides
the time priority internal to the ESCC. Systems using an external daisy chain must refer to
Note 5 of
If there is an interrupt pending in the ESCC, and IEI is High when DS falls, the acknowl-
edge cycle is intended for the ESCC. Consequently, the Z80230 sets the Interrupt Under
Service (IUS) latch for the highest priority pending interrupt, and places an interrupt vec-
INTACK
A7–A0
CS0
R/W
CS1
DS
AS
Table
45, for the time required to settle the daisy chain.
Figure 18. Z80230 Read Cycle Timing
Table 45
Address
on page 83, specify the setup and hold time requirements.
Figure
Data Valid
18. The register address on
Product Specification
Z80230 Interface Timing
Z80230/Z85230/L
Figure 19
on page
71