Z8523016VSC Zilog, Z8523016VSC Datasheet - Page 115

• Manufacturer Part Number: Z8523016VSC
• Description: IC 16MHZ ESCC 44-PLCC
• Manufacturer: Zilog

Specifications of Z8523016VSC

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3055

Index
A
abort character
absolute maximum ratings
AC characteristics
AC characteristics table, Z85230
AC characteristics, Z85230
asynchronous receive mode
auto echo and logical loopback
auto enable
automatic EOM reset
B
baud rate generator
bisync
block transfer, CPU/DMA
C
capacitance
character
code
command
counter
CRC problem
CRC reception in SDLC mode
Customer Feedback Form
PS005308-0609
abort
EOP
NRZ
NRZI
reset highest IUS
reset Tx CRC generator
reset Tx/underrun latch
transmit clock
description
solution
4, 16
18
18
18
18
4
76
104
18
104
78
5
19
28
28
112
75
15
87
28
4
28
26
21
90
P R E L I M I N A R Y
D
data communications capabilities
data encoding
DC characteristics
default RR0 value problem
default RR10 value problem
device type identification
diagram
description
solution
description
solution
40-pin DIP package
44-pin PLCC package
automatic RTS deactivation
cycle timing, Z85230
data encoding methods
detecting 5-or 7-bit characters
DPLL Outputs
ESCC protocols
general timing, Z80230
general timing, Z85230
interrupt acknowledge cycle timing, Z80230
interrupt acknowledge cycle timing, Z85230
interrupt acknowledge timing, Z80230
interrupt acknowledge timing, Z85230
interrupt priority schedule
read cycle timing, Z80230
read cycle timing, Z85230
read/write timing, Z80230
read/write timing, Z85230
receive data path
reset timing, Z80230
reset timing, Z85230
resetting highest IUS from lower priority
SDLC frame status FIFO
SDLC loop
standard and open-drain test conditions
system timing, Z80230
system timing, Z85230
transmit data path
TxIP latching
72
74
103
104
20
103
104
18
27
77
27
15
9
8
105
80
89
24
89
106
20
86
98
81
94
29
13
79
88
71
73
102
15
16
80
89
76
101
Index
108