Z8523316VSC Zilog, Z8523316VSC Datasheet - Page 8

• Manufacturer Part Number: Z8523316VSC
• Description: IC 16MHZ CMOS ESCC/2 44-PLCC
• Manufacturer: Zilog
• Series: EMSCC™r

Specifications of Z8523316VSC

• Controller Type: Serial Communications Controller (SCC)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -

AC CHARACTERISTICS
Z85233 Read and Write Timing Table
Notes:
[1] Parameter does not apply to Interrupt Acknowledge transactions.
[3] Parameter applies only between transactions involving the EMSCC.
[4] Open-drain output, measured with open-drain test load.
[5] Parameter is system dependent. For any EMSCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority
[6] Parameter applies to enhanced Request mode only (WR7' D4=1)
8
No
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35a TdWRr(REQ) /WR Fall to /DTR//REQ Not Valid
35b TdWRr(REQ) /WR Fall to /DTR//REQ Not Valid
36
37
38
39
40
41
42
43
44
45
46
47
48
49
device in the daisy chain. TsIEI(RDA) for the EMSCC and TdIEI(IEO) for each device separating them in the daisy chain.
Symbol
TsIAi(WR)
ThIA(WR)
TsIAi(RD)
ThIA(RD)
ThIA(PC)
TsCEI(WR)
ThCE(WR)
TsCEh(WR)
TsCEI(RD)
ThCE(RD)
TsCEh(RD)
TwRDI
TdRD(DRA)
TdRDr(DR)
TdRDI(DR)
TdRD(DRz)
TdA(DR)
TwWRI
TdWR(DW)
ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REQ) /WR Fall to /W//REQ Not Valid Delay
TdRDf(REQ)
TdRDr(REQ)
TdPC(INT)
TdIAi(RD)
TwRDA
TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEI(IEO)
TdPC(IEO)
TdRDA(INT)
TdRD(WRQ)
TdWRQ(RD)
TwRES
Trc
Parameter
/INTACK to /WR Fall Setup Time
/INTACK to /WR Rise Hold Time
/INTACK to /RD Fall Setup Time
/INTACK to /RD Rise Hold Time
/INTACK to PCLK Rise Hold Time
/CE Low to /WR Fall Setup Time
/CE to /WR Rise Hold Time
/CE High to /WR Fall Setup Time
/CE Low to /RD Fall Setup Time
/CE to /RD Rise Hold Time
/CE High to /RD Fall Setup Time
/RD Low Width
/RD Fall to Read Data Active Delay
/RD Rise to Data Not Valid Delay
/RD Fall to Read Data Valid Delay
/RD Rise to Read Data Float Delay
Addr to Read Data Valid Delay
/WR Low Width
/WR Fall to Write Data Valid Delay
Write Data to /WR Rise Hold Time
/WR Fall to Wait Valid Delay
/RD Fall to Wait Valid Delay
/RD Fall to /W//REQ Not Valid Delay
/RD Rise to /DTR//REQ Not Valid Delay
PCLK Fall to /INT Valid Delay
/INTACK to /RD Fall (Ack) Delay
/RD (Acknowledge) Width
/RD Fall(Ack) to Read Data Valid Delay
IEI to /RD Fall (Ack) Setup Time
IEI to /RD Rise (Ack) Hold Time
IEI to IEO Delay Time
PCLK Rise to IEO Delay
/RD Fall to /INT Inactive Delay
/RD Rise to /WR Fall Delay for No Reset
/WR Rise to /RD Fall Delay for No Reset
/WR and /RD Low for Reset
Valid Access Recovery Time
4TcPc
130
130
125
125
125
120
100
Min
30
50
50
90
95
15
15
0
0
0
0
0
0
0
0
0
0
10 MHz
2TcPC 70
4TcPc
Max Min
120
180
100
100
120
120
100
320
175
320
NA
35
20
90
4TcPc
70
70
15
30
30
75
50
75
70
50
10
10
75
0
0
0
0
0
0
0
0
0
0
16 MHz
2TcPC
4TcPc
Max
100
175
200
NA
70
20
50
50
70
70
70
45
80
30
Notes
[1]
[1]
[1]
[1]
[1]
[1]
[4]
[4]
[6]
[6]
[5]
[4]
[3]
CPS DC-4058-03
Z85233