MAX1887EEE Maxim Integrated Products, MAX1887EEE Datasheet - Page 25

• Manufacturer Part Number: MAX1887EEE
• Description: Current Mode PWM Controllers
• Manufacturer: Maxim Integrated Products

Specifications of MAX1887EEE

• Number Of Outputs: 1
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Switching Frequency: 550 KHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Synchronous Pin: No
• Topology: Boost

V
lower parasitic capacitance.
For the low-side MOSFET (N
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, “overdesign” the circuit to
tolerate:
where I
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-sized heatsink to handle the over-
load power dissipation.
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/(3
can be removed if efficiency is not critical.
The current balance compensation capacitor (C
integrates the difference of the master and slave cur-
rent-sense signals, while the compensation resistor
improves transient response by increasing the phase
margin. This allows the user to optimize the dynamics
of the current balance loop. Excessively large capacitor
values increase the integration time constant, resulting
in larger current differences between the phases during
transients. Excessively small capacitor values allow the
current loop to respond cycle by cycle but can result in
small DC current variations between the phases.
Likewise, excessively large series resistance can also
cause DC current variations between the phases. Small
series resistance reduces the phase margin, resulting
in marginal stability in the current balance loop. For
most applications, a 470pF capacitor and 10kΩ series
resistor from COMP to the converter’s output voltage
works well.
The compensation network can be tied to V
include the feed-forward term due to the master’s on
time (see the On-time Control and Active Current
LOAD(MAX)
IN(MAX)
PD N
(
Current Balance Compensation (COMP)
L
I
η
LOAD
) of the load current. This diode is optional and
Re
VALLEY(MAX)
, consider choosing another MOSFET with
sistive
but are not quite high enough to exceed
=
η
I
)
VALLEY MAX
=
______________________________________________________________________________________




1
−
is the maximum valley current



(
V
IN MAX
V
OUT
(
)
L
+
), the worst-case power



)
I



LOAD MAX







I
LOAD
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
(
η
2



)
2
LIR
R
DS ON



(
OUT
COMP
)
to
)
Balancing section). To reduce noise pick-up in applica-
tions that have a widely distributed layout, it is some-
times helpful to connect the compensation network to
quiet analog ground rather than V
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissi-
pation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power require-
ments. After a load transient, the output instantly
changes by ESR
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 7). However, the CPU only requires that the out-
put voltage remain above a specified minimum value.
Dynamically positioning the output voltage to this lower
limit allows the use of fewer output capacitors and
reduces power consumption under load.
For a conventional (nonvoltage-positioned) circuit, the
total voltage change is:
where V
the converter to regulate at a lower voltage when under
load allows a larger voltage step when the output cur-
rent suddenly decreases (Figure 7). So the total voltage
change for a voltage-positioned circuit is:
where V
Procedure section. Since the amplitudes are the same
for both circuits (V
circuit tolerates twice the ESR. Since the ESR specifica-
tion is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Since the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
R
72.7mΩ), reducing the output voltage 2.9% gives an
output voltage of 1.55V and an output current of 21.3A.
Given these values, CPU power consumption is
reduced from 35.2W to 33.03W. The additional power
consumption of R
SENSE
V
P-P
V
P-P
1 = 2
SAG
. For a nominal 1.6V, 22A output (R
2 = (ESR
SAG
✕
and V
and V
(ESR
Applications Information
COUT
SENSE
COUT
P-P
SOAR
COUT
SOAR
1 = V
✕
✕
is:
are defined in Figure 8. Setting
Voltage Positioning and
∆I
✕
∆I
P-P
are defined in the Design
∆I
LOAD
LOAD
LOAD
2), the voltage-positioned
Effective Efficiency
. Conventional DC-DC
) + V
OUT
) + V
.
SAG
SAG
+ V
+ V
SOAR
LOAD
SOAR
25
=