MAX1847EEE Maxim Integrated Products, MAX1847EEE Datasheet - Page 14

• Manufacturer Part Number: MAX1847EEE
• Description: Current Mode PWM Controllers
• Manufacturer: Maxim Integrated Products

Specifications of MAX1847EEE

• Case: ssop
• Dc: 05+
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

High-Efficiency, Current-Mode,
Inverting PWM Controller
tance as possible. For continuous inductor current, the
power loss in the inductor resistance (P
mated by:
where R
Once the peak inductor current is calculated, the cur-
rent sense resistor, R
For high peak inductor currents (>1A), Kelvin-sensing
connections should be used to connect CS and PGND
to R
ground side of R
CS may be required to prevent switching noise from
tripping the current-sense comparator at heavy loads.
Connect a 100Ω resistor between CS and the high side
of R
and GND.
In a current-mode regulator, the cycle-by-cycle stability
is dependent on slope compensation to prevent sub-
harmonic oscillation at duty cycles greater than 50%.
For the MAX1846/MAX1847, the internal slope compen-
sation is optimized for a minimum inductor value (L
with respect to duty cycle. For duty cycles greater then
50%, check stability by calculating LMIN using the fol-
lowing equation:
where V
M
D
larger than L, increase the value of L to the next stan-
dard value that is larger than L
compensation stability.
Choosing the most cost-effective inductor usually
requires optimizing the field and flux with size. With
higher output voltages the inductor may require many
turns, and this can drive the cost up. Choosing an
inductor value at L
discontinuous inductor current can be tolerated.
Powdered iron cores can provide the most economical
solution but are larger in size than ferrite.
14
MAX
s
is the Slope Compensation Ramp (41 mV/µs) and
CS
Checking Slope-Compensation Stability
______________________________________________________________________________________
CS
is the maximum expected duty cycle. If L
, and connect a 1000pF capacitor between CS
. Connect PGND and GND together at the
L
IN(MIN)
L
is the inductor series resistance.
MIN
=
x
P
LR
is the minimum expected input voltage,
⎡
⎣ ⎢
CS
⎡
⎣ ⎢
R
(
(
V
2
CS
~
IN MIN
MIN
. A lowpass filter between R
Choosing the Inductor Core
x D
CS
(
R x
= 85mV / I
L
, is determined by:
can provide a good solution if
MAX
)
⎛
⎜
⎝
x R
I
−
−
I
1
CS
LOAD
) (
LPEAK
D
/
)
MAX
MIN
/
1
M
−
D
S
⎞
⎟
⎠
to ensure slope
⎤
⎦ ⎥
MAX
2
LR
) is approxi-
)
⎤
⎦ ⎥
CS
MIN
MIN
and
is
)
The MAX1846/MAX1847 drive a wide variety of P-chan-
nel power MOSFETs (PFETs). The best performance,
especially with input voltages below 5V, is achieved
with low-threshold PFETs that specify on-resistance
with a gate-to-source voltage (V
When selecting a PFET, key parameters include:
• Total gate charge (Q
• Reverse transfer capacitance (C
• On-resistance (R
• Maximum drain-to-source voltage (V
• Minimum threshold voltage (V
At high-switching rates, dynamic characteristics (para-
meters 1 and 2 above) that predict switching losses
may have more impact on efficiency than R
which predicts DC losses. Q
associated with charging the gate. In addition, this
parameter helps predict the current needed to drive the
gate at the selected operating frequency. The power
MOSFET in an inverting converter must have a high
enough voltage rating to handle the input voltage plus
the magnitude of the output voltage and any spikes
induced by leakage inductance and ringing.
An RC snubber circuit across the drain to ground might
be required to reduce the peak ringing and noise.
Choose R
one to two times R
and V
and fall-times (t
The output capacitor (C
inverting converter. The output ripple is created by the
variations in the charge stored in the output capacitor
with each pulse and the voltage drop across the
capacitor’s equivalent series resistance (ESR) caused
by the current into and out of the capacitor. There are
two properties of the output capacitor that affect ripple
voltage: the capacitance value, and the capacitor’s
ESR. The output ripple due to the output capacitor’s
value is given by:
The output ripple due to the output capacitor’s ESR is
given by:
These two ripple voltages are additive and the total out-
put ripple is:
V
DS(MAX)
RIPPLE-C
DS(ON)(MAX)
V
RIPPLE-T
> V
R
V
, t
= (I
RIPPLE-R
F
IN(MAX)
) to be less than 50ns.
DS(ON)
CS
LOAD
Output Capacitor Selection
= V
. Verify that V
specified at V
Power MOSFET Selection
G
RIPPLE-C
OUT
)

- V
)
= I
D
) does all the filtering in an
OUT
G
LPP
MAX
includes all capacitance
TH(MIN)

+ V
+ V

RSS
GS
R
IN(MAX)
T
GS
ESR
D
RIPPLE-R
OSC
) of 2.7V or less.
. Choose the rise-
)
DS(MAX)
)
< V
) / C
IN(MIN)
< V
OUT
)
GS(MAX)
DS(ON
to be
),