DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 14

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

Figure 5c ) Parameter t
DP8419 Mode Descriptions
Page or Nibble mode may be performed by toggling CASIN
once the initial access has been completed In the case of
page mode the column address must be changed before
CASIN goes low to access a new memory location (see
users may easily determine minimum CAS pulse widths
when CASIN is toggling
AUTOMATIC CAS GENERATION
CAS is held high when R C is high even if CASIN is low If
CASIN is low when R C goes low CAS goes low automati-
cally t
eliminates the need for an externally derived CASIN signal
to control CAS when performing a simple access ( Figure 5a
demonstrates Auto-CAS generation in mode 4) Page or nib-
ble accessing may be performed as shown in Figure 5c
even if CAS is generated automatically for the initial access
FASTEST MEMORY ACCESS
The fastest mode 4 access is achieved by using the auto-
matic CAS feature and external delay line to generate the
required delay between RASIN and R C The amount of
delay required depends on the minimum t
being used The DP8419 parameter t
fied in order that the delay between RASIN and R C may be
minimized
The delay between RASIN and R C that guarantees the
specified DRAM t
Example
In an application using DRAMs that require a minimum t
of 15 ns the following demonstrates how the maximum
RASIN to CAS time is determined
where t
ASC
and t
MINIMUM RASIN to R C
after the column address is valid This feature
t
RPDL
DIF1
RHA
RAH
e
e
e
MAXIMUM (t
row address held from R C going low
RASIN to RAS delay
is given by
CPdif
has been specified in order that
RPDL
e
t
DIF1
DIF1
FIGURE 5c Page or Nibble Access in Mode 4
- t
RAH
RHA
a
has been speci-
t
of the DRAMs
(Continued)
)
RAH
RAH
14
With t
A delay line of 25 ns will be sufficient
With Auto-CAS generation the maximum delay from R C to
CAS (loaded with 600 pF) is 46 ns Thus the maximum
RASIN to CAS time is 71 ns under the given conditions
With a maximum RASIN to RAS time (t
maximum RAS to CAS time is about 51 ns Most DRAMs
with a 15 ns minimum t
60 ns Thus memory accesses are likely to be RAS limited
instead of CAS limited In other words memory access time
is limited by DRAM performance not controller perform-
ance
REFRESHING IN CONJUNCTION WITH MODE 4
If using mode 4 to access memory mode 0 (externally con-
trolled refresh) must be used for all refreshing
MODE 5 – AUTOMATIC ACCESS WITH HIDDEN RE-
FRESHING CAPABILITY
Automatic-Access has two advantages over the externally
controlled access (mode 4) First RAS CAS and the row to
column change are all derived internally from one input sig-
nal RASIN Thus the need for an external delay line (see
mode 4) is eliminated
Secondly since R C and CASIN are not needed to gener-
ate the row to column change and CAS these pins can be
used for the automatic refreshing function
AUTOMATIC ACCESS CONTROL
Mode 5 of the DP8419 makes accessing Dynamic RAM
nearly as easy as accessing static RAM Once row and col-
umn addresses are valid (latched on the DP8419 if neces-
sary) RASIN going low is all that is required to perform the
memory access
DIF1
RASIN to R C delay
(from Switching Characteristics)
RAH
e
have a maximum t
7 ns
a
15 ns
RPDL
e
e
) of 20 ns the
TL F 8396 – 15
7 ns
RCD
22 ns
of about