DP8420AV-25 National Semiconductor, DP8420AV-25 Datasheet - Page 44
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DP8420AV-25
Manufacturer Part Number
DP8420AV-25
Description
IC CTRLR 256K DRAM PROG 68PLCC
Manufacturer
National Semiconductor
Datasheet
1.DP8420AV-25.pdf
(58 pages)
Specifications of DP8420AV-25
Controller Type
Dynamic RAM (DRAM) Controller, Drivers
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Voltage - Supply
-
Operating Temperature
-
Interface
-
Other names
*DP8420AV-25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP8420AV-25
Manufacturer:
NSC
Quantity:
1 831
Number
21
22
23
24
25
26
27
28
29a
29b
30
31
32
33
34a
34b
34c
34d
35
36
13 0 AC Timing Parameters
Unless otherwise stated V
per bank including trace capacitance (Note 2)
Two different loads are specified
C
C
L
L
e
e
50 pF loads on all outputs except
150 pF loads on Q0–8 9 10 and WE or
tPEDL
tPEDH
tSWCK
tPWINWEH WIN Asserted to WE Asserted
tPWINWEL
tPAQ
tPCINCQ
tSCINEN
tSARQCK1
tSARQCK2
tPAREQDH AREQ Negated to DTACK Negated
tPCKCAS
tSCADEN
tWCINC
tPCKCL0
tPCKCL1
tPCKCL2
tPCKCL3
tCAH
tPCQR
Symbol
ECAS Asserted to DTACK
Asserted during a Burst Access
(Programmed as DTACK0)
ECAS Negated to DTACK
Negated during a Burst Access
WAITIN Asserted Setup to CLK
WIN Negated to WE Negated
Row Column Address Valid to
Q0–8 9 10 Valid
COLINC Asserted to Q0–8 9 10
Incremented
COLINC Asserted Setup to ECAS
Asserted to Ensure tASC
AREQ AREQB Negated Setup to CLK
High with 1 Period of Precharge
AREQ AREQB Negated Setup to CLK High
with
CLK High to CAS Asserted
when Delayed by WIN
Column Address Setup to ECAS
Asserted to Guarantee tASC
COLINC Pulse Width
CLK High to CAS Asserted following
Precharge (tRAH
CLK High to CAS Asserted following
Precharge (tRAH
CLK High to CAS Asserted following
Precharge (tRAH
CLK High to CAS Asserted following
Precharge (tRAH
Column Address Hold Time
(Interleave Mode Only)
CAS Asserted to Row Address
Valid (Interleave Mode Only)
CC
l
1 Period of Precharge Programmed
e
5 0V
Common Parameter
g
Description
10% 0 C
e
e
e
e
15 ns tASC
15 ns tASC
25 ns tASC
25 ns tASC
(Continued)
e
k
0 ns
e
T
A k
0
e
e
e
e
70 C the output load capacitance is typical for 4 banks of 18 DRAMs
0 ns)
10 ns)
0 ns)
10 ns)
44
C
C
C
Min
H
H
H
18
46
19
14
20
32
5
e
e
e
8420A 21A 22A-20
C
50 pF loads on all outputs except
125 pF loads on RAS0– 3 and CAS0–3 and
380 pF loads on Q0– 8 9 10 and WE
L
Max
101
48
49
34
34
29
34
34
31
81
91
91
90
Min
19
46
19
15
20
32
5
C
H
Max
109
48
49
44
44
38
43
34
39
89
99
99
90
Min
17
37
15
14
20
32
5
8420A 21A 22A-25
C
L
Max
38
38
27
27
26
30
27
25
72
82
82
92
90
Min
19
37
15
16
20
32
5
C
H
Max
38
38
37
37
35
39
27
32
79
89
89
99
90