DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 7

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

1 0 Functional Description
Serializer After data has been written into the 32-byte
transmit FIFO the serializer reads byte wide data from the
FIFO and sends a NRZ data stream to the Manchester en-
coder The rate at which data is transmitted is determined
by the transmit clock (TXC) The serialized data is transmit-
ted after the SFD
Preamble Generator The preamble generator prefixes a 7
byte alternating ‘‘1 0’’ pattern and a 1 byte ‘‘10101011’’
SFD pattern at the beginning of each packet This allows
receiving nodes to synchronize to the incoming data The
preamble is always transmitted in its entirety even in the
event of a collision This assures that the minimum collision
fragment is 96 bits (64 bits of normal preamble and 4 bytes
or rather 32 bits of the JAM pattern)
CRC Generator The CRC generator calculates the 4-byte
FCS field from the transmitted serial data stream If en-
abled the 4-byte FCS field is appended to the end of the
transmitted packet (Section 2 6)
For bridging or switched ethernet applications the CRC
Generator can be inhibited by setting bit 13 in the Transmit
Control Register (Section 4 3 4) This feature is used when
an ethernet segment has already received a packet with a
CRC appended and needs to forward it to another ethernet
segment
Jam Generator The Jam generator produces a 4-byte pat-
tern of all 1’s to assure that all nodes on the network sense
the collision When a collision occurs the SONIC stops
transmitting data and enables the Jam generator If a colli-
sion occurs during the preamble the SONIC finishes trans-
mitting the preamble before enabling the Jam generator
(see Preamble Generator above)
1 3 DATA WIDTH AND BYTE ORDERING
The SONIC can be programmed to operate with either
32-bit or 16-bit wide memory The data width is configured
during initialization by programming the DW bit in the Data
Configuration Register (DCR Section 4 3 2) If the 16-bit
data path is selected data is driven on pins D15– D0 The
SONIC also provides both Little Endian and Big Endian
(Continued)
FIGURE 1-5 Receive FIFO
7
byte-ordering capability for compatibility with National Intel
or Motorola microprocessors respectively by selecting the
proper level on the BMODE pin The byte ordering is depict-
ed below
Little Endian mode (National Intel BMODE
byte orientation for received and transmitted data in the Re-
ceive Buffer Area (RBA) and Transmit Buffer Area (TBA) of
system memory is as follows
Big Endian mode (Motorola BMODE
entation for received and transmitted data in the RBA and
TBA is as follows
15
15
31
31
Byte 1
Byte 3
Byte 0
Byte 0
MSB
MSB
LSB
LSB
16-Bit Word
16-Bit Word
24
24
8
8
7
23
7
23
Byte 0
Byte 2
Byte 1
Byte 1
MSB
LSB
32-Bit Long Word
32-Bit Long Word
16
16
0
0
15
15
Byte 1
Byte 2
e
8
8
TL F 10492 – 6
1) The byte ori-
7
7
e
Byte 0
Byte 3
MSB
LSB
0) The
0
0