DP83932CVF-25 National Semiconductor, DP83932CVF-25 Datasheet - Page 53

• Manufacturer Part Number: DP83932CVF-25
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-25

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-25

Figures 5-5 and 5-6 show the National Intel (BMODE
5 0 Bus Interface
5 4 1 Acquiring The Bus
The SONIC requests the bus when 1) its FIFO threshold has
been reached or 2) when the descriptor areas in memory
(i e RRA RDA CDA and TDA) are accessed Note that
when the SONIC moves from one area in memory to anoth-
er (e g RBA to RDA) it always deasserts its bus request
and then requests the bus again when accessing the next
area in memory
The SONIC provides two methods to acquire the bus for
compatibility with National Intel or Motorola type microproc-
essors These two methods are selected by setting the
proper level on the BMODE pin
and Motorola (BMODE
tions of each mode follows For both modes when the
SONIC relinquishes the bus there is an extra holding state
(Th) for one bus cycle after the last DMA cycle (T2) This
assures that the SONIC does not contend with another bus
master after it has released the bus
BMODE
The National Intel processors require a 2-way handshake
using a HOLD REQUEST HOLD ACKNOWLEDGE protocol
( Figure 5-5 ) When the SONIC needs to access the bus it
issues a HOLD REQUEST (HOLD) to the microprocessor
The microprocessor responds with a HOLD ACKNOWL-
EDGE (HLDA) to the SONIC The SONIC then begins its
memory transfers on the bus As long as the CPU maintains
HLDA active the SONIC continues until it has finished its
memory block transfer The CPU however can preempt the
SONIC from finishing the block transfer by deasserting
HLDA before the SONIC deasserts HOLD This allows a
higher priority device to preempt the SONIC from continuing
to use the bus The SONIC will request the bus again later
to complete any operation that it was doing at the time of
preemption The HLDA signal is sampled synchronously by
the SONIC at the rising edge of the BSCK setup time must
be met to ensure proper operation
e
0
e
1) bus request timing Descrip-
(Continued)
FIGURE 5-5 Bus Request Timing BMODE
e
0)
53
As shown in Figure 5-5 the SONIC will assert HOLD to
either the falling or rising edge of the bus clock (BSCK) The
default is for HOLD to be asserted on the falling edge Set-
ting the PH bit in the DCR2 (see Section 4 3 7) causes
HOLD to be asserted
(shown by the dotted line) Before HOLD is asserted the
SONIC checks the HLDA line If HLDA is asserted HOLD
will not be asserted until after HLDA has been deasserted
first
Note If HLDA is driven low to preempt the SONIC from the bus while the
BMODE
The Motorola protocol requires a 3-way handshake using a
BUS REQUEST BUS GRANT and BUS GRANT AC-
KNOWLEDGE handshake ( Figure 5-6 ) When using this
protocol the SONIC requests the bus by lowering BUS RE-
QUEST (BR) The CPU responds by issuing BUS GRANT
(BG) Upon receiving BG the SONIC assures that all devic-
es have relinquished control of the bus before using the
bus The following signals must be deasserted before the
SONIC acquires the bus
Deasserting BGACK indicates that the previous master has
released the bus Deasserting AS indicates that the previ-
ous master has completed its cycle and deasserting
DSACK0 1 and STERM indicates that the previous slave
has terminated its connection to the previous master The
SONIC maintains its mastership of the bus until it deasserts
BGACK It cannot be preempted from the bus
BGACK
AS
DSACK0 1
STERM (Asynchronous Mode Only)
SONIC is accessing the CAM (LCAM command) the SONIC will get
off the bus but will not deassert HOLD even though the status bit will
indicate idle state If HLDA is driven low while the SONIC is accessing
descriptor areas (RRA RDA TDA) the SONIC will be preempted
normally (i e get off the bus and deassert HOLD) and the HOLD
signal will be reasserted again after one bus clock If HLDA is driven
low while the SONIC is accessing data areas (RBA TBA) the SONIC
will be preempted normally but may not reassert HOLD unless re-
quired to do so depending on the threshold condition of the FIFO
e
1
e
0
bus clock later on the rising edge
TL F 10492 – 27