MC33389CDH Freescale Semiconductor, MC33389CDH Datasheet - Page 34

• Manufacturer Part Number: MC33389CDH
• Description: IC SYSTEM BASIS W/CAN 20-HSOP
• Manufacturer: Freescale Semiconductor

Specifications of MC33389CDH

• Controller Type: Systems Basis Chip (SBC), CAN
• Interface: SPI Serial
• Voltage - Supply: 5V
• Current - Supply: 3.5mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-HSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Safety Concept
any data fault detection capabilities, the SPI interface of the
33389 provides built-in fail save functions.
distance, parity check, and parity generation for data.
Hamming distance < 2 will be used. So, any single bit failure
caused by disturbances will be recognized and handled.
When one bit toggles in the address field during the
transmission, no misbehavior occurs.
confirm safety critical settings in the 33389, e.g. the Mode
Control Register MCR has its validation register, MCVR. To
change the appropriate settings, both registers must have the
same content to switch to another mode.
module in the 33389 ascertains the parity of the data field and
compares the result with the received parity. When the parity
check is successfully passed, data will be written into the
addressed registers. The parity bits P3 to P0 results from the
logic following equations:
Table 17. Mode Control Register (MCR)
34
33389
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Address
Because the SPI interface is an on-board interface without
Address coding is based on increasing the Hamming
For the address and the read/write bits, only codes with a
Additionally, validation registers are implemented to
To increase data integrity, a parity check is used. A parity
RESET
MCR
$000
HC08/12 SPI Data Register
A5 A4
P3 P2
Bit7
Bit7
Bit6
Bit6
new parity + new data in
HC08/12 SPI read buffer
Bit5
A3 A2 A1 A0
Bit5
P1 P0 D3 D2 D1 D0
W
R
Bit4
Bit4
Bit3
Bit3
Bit 7
Bit2
Bit2
—
Bit1
Bit1
0
Figure 21. Microcontroller SPI Reading Data - Sequence C
Bit0
Bit0
0
Bit 6
—
Bit 5
—
SBC SPI Data Register
Bit15
A5 A4 A3 A2 A1 A0
Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
old address + R/W
Bit 4
—
the SBC and an error flag is set in an SPI register.
SPI REGISTERS DESCRIPTIONS
change the operating mode of the SBC, both registers must
have the same content. The order of writing the registers has
to be taken into account. To properly set the SBC mode,
MCR must be written first followed by the MCVR write. A write
operation sets the MCR and MCVR registers.
RST = low and the SBC is set to Normal Request mode.
Registers MCR and MCVR control the SBC mode. To
The Emergency mode is a regular mode.
A reset of both MCR and MCVR registers occurs when
In case of error detection, the incoming data is not taken in
RW
Bit 3
—
P3 = D3 ⊕ D0
P2 = D3 ⊕ D2
P1 = D2 ⊕ D1
P0 = D1 ⊕ D0
RW
Bit8
Bit7
0
Analog Integrated Circuit Device Data
old parity
Bit6
MCR2
MSR2
0
Bit 2
0
Bit5
0
Bit4
0
Freescale Semiconductor
Bit3
(EX - OR)
0
MCR1
MSR1
Bit 1
0
old data
Bit2
0
Bit1
0
Bit0
0
MSR0
MCR0
Bit 0
0