CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 56

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
8
7
6
5
4
3
BIT
PMD Loopback
Strip Preamble
Alternate FDX CRS Read/Write 0
Loopback Transmit
Disable
Code Error Report
Select
Premature End
Error Report Select
NAME
Read/Write 0
Read/Write 0
Read/Write 1
Read/Write 0
Read/Write 0
TYPE
RESET
When set, the scrambled NRZI transmit data is con-
nected directly to the NRZI receive port on the
descrambler. The loopback includes all of the
100BASE-TX functionality except for the MLT-3
encoding/decoding and the analog line-interface
blocks. When clear, the CS8952 is configured for
normal operation.
Note: Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
When set this bit causes the 7 bytes of MAC pream-
ble to be stripped off of incoming 100 Mb/s frames.
The data received across the MII will begin with the 1
byte Start of Frame Delimiter (SFD).
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
the full-duplex (FDX) mode of operation. When set,
CRS will be asserted for transmit data only. When
clear, CRS will be asserted only for receive data.
This bit controls whether loopback data is transmitted
onto the network. When set, any data transmitted
during PMD or ENDEC loopback mode will NOT be
transmitted onto the network. When clear, data will
be transmitted on the TX+/- pins as well as looped
back onto the MII pins.
When set, this bit causes code errors to be reported
by a value of 5h on RXD[3:0] and the assertion of
RX_ER.
When clear, this bit causes code errors to be
reported by a value of 6h on RXD[3:0] and the asser-
tion of RX_ER.
This bit is superseded by the Code Error Report
Enable bit.
When set, this bit causes premature end errors to be
reported by a value of 4h on RXD[3:0] and the asser-
tion of RX_ER.
When clear, this bit causes premature end errors to
be reported by a value of 6h on RXD[3:0] and the
assertion of RX_ER.
A premature end error is caused by the detection of
two IDLE symbols in the 100 Mb/s receive data
stream prior to the End of Stream Delimiter.
This bit changes the behavior of the CRS pin only in
DESCRIPTION
CS8952
56