KSZ8721B TR Micrel Inc, KSZ8721B TR Datasheet - Page 6

• Manufacturer Part Number: KSZ8721B TR
• Description: IC TXRX PHY 10/100 2.5V 48SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721B TR

• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1627 - BOARD EVALUATION FOR KSZ8721BMC576-1626 - BOARD EVALUATION FOR KSZ8721BL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1026-2

KS8721B/BT
Pin Description
Note 1.
M9999-041405
Pin Number
10
11
12
13
14
15
16
17
18
19
20
21
24
1
2
3
4
5
6
7
8
9
Pwr = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Gnd = ground
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
NC = No connect
PCS_LPBK
RXER/ISO
Pin Name
COL/RMII
PHYAD1
PHYAD2
PHYAD3
PHYAD4
REFCLK
CRSDV/
VDDIO
VDDIO
RXDV/
RXD3/
RXD2/
RXD1/
RXD0/
VDDC
MDIO
TXER
TXEN
TXD0
TXD1
TXD2
TXD3
MDC
GND
GND
TXC/
RXC
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipd/O
GND
GND
Pwr
Pwr
Pwr
I/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
O
(Note 1)
I
Pin Function
Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up
resistor.
Management Interface (MII) Clock Input: This pin is synchronous to the MDIO
data interface
MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is
latched as PHYADDR [1] during reset. See “Strapping Options” section for
details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2]
during reset. See “Strapping Options” section for details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3]
during reset. See “Strapping Options” section for details.
MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4]
during reset. See “Strapping Options” section for details.
Digital IO 2.5 /3.3V tolerance power supply.
Ground.
MII Receive Data Valid Output: The pull-up/pull-down value is latched as
pcs_lpbk during reset. See “Strapping Options” section for details.
MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE
during reset. See “Strapping Options” section for details.
Ground.
Digital core 2.5V only power supply.
MII Transmit Error Input.
MII Transmit Clock Output: RMII Reference Clock Input.
MII Transmit Enable Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Transmit Data Input
MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select
during reset. See “Strapping Options” section for details.
Digital IO 2.5/3.3V tolerance power supply.
6
Micrel, Inc.
April 2005