KSZ8721B Micrel Inc, KSZ8721B Datasheet - Page 9

• Manufacturer Part Number: KSZ8721B
• Description: IC TXRX PHY 10/100 2.5V 48-SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721B

• Number Of Drivers/receivers: 1/1
• Protocol: MII, RMII
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Data Rate: 100Mbps
• Supply Voltage Range: 2.375V To 2.625V
• Logic Case Style: SSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 2 - 1 Year
• Ic Function: Transceiver IC
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1627 - BOARD EVALUATION FOR KSZ8721BMC576-1626 - BOARD EVALUATION FOR KSZ8721BL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1026-5; 576-1510-5; 576-1510-5; KSZ8721B

Strapping Options
Note 1.
Note 2.
Note 3.
April 2005
KS8721B/BT
Pin Number
11
21
22
6,5,
9
4,3
25
27
28
29
30
(3)
(3)
(3)
(3)
Strap-in is latched during power-up or reset.
Ipu = input w/ internal pull-up
Ipd = input w/ internal pull-down
Ipd/O = input w/ internal pull-down during reset, output pin otherwise
Ipu/O = input w/ internal pull-up during reset, output pin otherwise
PU = strap pin pull-up
PD = strap pin pull-down
Some devices may drive MII pins that are designated as output (PHY) on power up, resulting in incorrect strapping values latched in at reset.
It is rcommended that an external pull down via 1kΩ resistor be used in these applications to augment the 8721's internal pull down.
PHYAD[4:1]/
PCS_LPBK/
ISO/RXER
NWAYEN/
Pin Name
RMII_BTB
RMII/COL
PHYAD0/
DUPLEX/
RXD[0:3]
SPD100/
No FEF/
RXDV
LED1
LED2
LED3
INT#
CRS
PD#
(Note 1)
Type
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu
(Note 2)
Description
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII_BTB mode at power-up/reset. PD (default) = Disable, PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default)
= 100Mbps. If SPD100 is asserted during power-up/reset, this pin also latched as
the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half duplex, PU
(default) = Full duplex. If Duplex is pulled up during reset, this pin also latched as
the Duplex support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/
reset. PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power Down Enable. PU (default) = Normal operation, PD = Power down mode.
9
M9999-041405
Micrel, Inc.