CLC007BM/NOPB National Semiconductor, CLC007BM/NOPB Datasheet - Page 7

• Manufacturer Part Number: CLC007BM/NOPB
• Description: IC CABLE DRIVER SERIAL 8SOIC
• Manufacturer: National Semiconductor
• Series: CLCr
• Type: Driverr

Specifications of CLC007BM/NOPB

• Number Of Drivers/receivers: 1/0
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Device Type: Line
• Propagation Delay: 1ns
• Supply Voltage Range: 4.5V To 5.5V
• Driver Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Base Number: 7
• Number Of Channels Per Chip: 1
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Current: 39 mA
• Operating Voltage: 5 V
• For Use With: SD007EVK - BOARD EVALUATION CLC007
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Protocol: -
• Lead Free Status / Rohs Status: Details
• Other names: CLC007BM

OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or other-
wise, may be reduced by placing the output back-match
PCB Layout Recommendations
Printed circuit board layout affects the performance of the
CLC007. The following guidelines will aid in achieving satis-
factory device performance.
•
•
•
Use a ground plane or power/ground plane sandwich
design for optimum performance.
Bypass device power with a 0.01 µF monolithic ceramic
capacitor in parallel with a 6.8 µF tantalum electrolytic
capacitor located no more than 0.1” (2.5 mm) from the
device power pins.
Provide short, symmetrical ground return paths for:
FIGURE 7. Differential Input DC Coupled Output
FIGURE 8. Rise Time vs C
7
resistor close to the output pin and by minimizing all intercon-
necting trace lengths. Figure 8 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
•
— inputs,
— supply bypass capacitors and
— the output load.
Provide short, grounded guard traces located
— under the centerline of the package,
— 0.1” (2.5 mm) from the package pins
— on both top and bottom of the board with connecting
vias.
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