MCP2515-I/SO Microchip Technology Inc., MCP2515-I/SO Datasheet
MCP2515-I/SO
Specifications of MCP2515-I/SO
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MCP2515-I/SO Summary of contents
Page 1
... Controller Area Network (CAN) controller that imple- ments the CAN specification, version 2.0B capable of transmitting and receiving both standard and extended data and remote frames. The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead ...
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... MCP2515 NOTES: DS21801D-page 2 Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. 1.2 Control Logic The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. Interrupt pins are provided to allow greater system flexibility. There is one multi-purpose interrupt pin (as ...
Page 4
... Chip select input pin for SPI interface I Active low device reset input P Positive supply for logic and I/O pins No internal connection Preliminary Node Controller SPI MCP2515 TX RX XCVR Alternate Pin Function — — Start-of-Frame signal General purpose digital input. 100 k internal pull- General purpose digital input ...
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... Transmit/Receive Buffers/Masks/Filters The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. Figure 1-3 shows a block diagram of these buffers and their connection to the protocol engine. FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM ...
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... MCP2515 1.5 CAN Protocol Engine The CAN protocol engine combines several functional blocks, shown in Figure 1-4 and described below. 1.5.1 PROTOCOL FINITE STATE MACHINE The heart of the engine is the Finite State Machine (FSM). The FSM is a sequencer that controls the sequential data stream between the TX/RX shift register, the CRC register and the bus line ...
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... CAN MESSAGE FRAMES The MCP2515 supports standard data frames, extended data frames and remote frames (standard and extended), as defined in the CAN 2.0B specification. 2.1 Standard Data Frame The CAN standard data frame is shown in Figure 2-1. As with all other frames, the frame begins with a Start- Of-Frame (SOF) bit, which is of the dominant state and allows hard synchronization of all nodes ...
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... Note: Case 2 should never occur with the MCP2515 due to very short internal delays. 2.6 Interframe Space The interframe space separates a preceding frame (of any type) from a subsequent data or remote frame. ...
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... FIGURE 2-1: STANDARD DATA FRAME © 2005 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 Bit Reserved IDE RTR ID0 ID3 10 ID Start-of-Frame Preliminary MCP2515 DS21801D-page 9 ...
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... MCP2515 FIGURE 2-2: EXTENDED DATA FRAME DS21801D-page 10 Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR EID0 EID17 IDE SRR ID0 ID3 ID10 Start-Of-Frame Preliminary © 2005 Microchip Technology Inc. ...
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... FIGURE 2-3: REMOTE FRAME © 2005 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR EID0 EID17 IDE SRR ID0 ID3 ID10 Start-Of-Frame Preliminary MCP2515 DS21801D-page 11 ...
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... MCP2515 FIGURE 2-4: ACTIVE ERROR FRAME Start-Of-Frame DS21801D-page 12 DLC0 DLC3 RB0 Bit Reserved IDE RTR ID0 ID3 10 ID Preliminary © 2005 Microchip Technology Inc. ...
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... FIGURE 2-5: OVERLOAD FRAME © 2005 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 IDE RTR ID0 10 ID Start-Of-Frame Preliminary MCP2515 DS21801D-page 13 ...
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... MCP2515 NOTES: DS21801D-page 14 Preliminary © 2005 Microchip Technology Inc. ...
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... Transmit Priority Transmit priority is a prioritization within the MCP2515 of the pending transmittable messages. This is independent from, and not necessarily related to, any prioritization implicit in the message arbitration scheme built into the CAN protocol. ...
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... Configuration and control of these pins is accomplished using the TXRTSCTRL register (see Register 3-2). The TXRTSCTRL register can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). If configured to operate as a request-to-send pin, the pin is mapped into the respective TXBnCTRL ...
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... CTRL.ABAT bit before the message has started transmission, will abort the message TXBnCTRL.TXREQ=0 or CANCTRL.ABAT=1 ? Yes Yes Message error Was No or Lost arbitration ? Lost Arbitration Set TxB CTRL.MLOA N No Set Preliminary MCP2515 No Message Error Set TxBnCTRL.TXERR Yes CANINTE.MEERE? No Generate Interrupt Set CANTINF.MERRF DS21801D-page 17 ...
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... MCP2515 REGISTER 3-1: TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER (ADDRESS: 30h, 40h, 50h) U-0 — ABTF bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 ABTF: Message Aborted Flag bit 1 = Message was aborted 0 = Message completed transmission successfully bit 5 MLOA: Message Lost Arbitration bit ...
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... Bit is cleared R/W-x R/W-x R/W-x SID8 SID7 SID6 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R/W-0 R/W-0 R/W-0 B2RTSM B1RTSM B0RTSM bit Bit is unknown R/W-x R/W-x R/W-x SID5 SID4 ...
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... MCP2515 REGISTER 3-4: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW (ADDRESS: 32h, 42h, 52h) R/W-x R/W-x SID2 SID1 bit 7 bit 7-5 SID: Standard Identifier bits <2:0> bit 4 Unimplemented: Reads as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended identifier ...
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... R/W-x TXBnDm TXBnDm TXBnDm Transmit Buffer n Data Field Bytes Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R/W-x R/W-x R/W-x DLC2 DLC1 DLC0 bit Bit is unknown R/W-x R/W-x R/W-x TXBnDm TXBnDm TXBnDm ...
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... MCP2515 NOTES: DS21801D-page 22 Preliminary © 2005 Microchip Technology Inc. ...
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... MESSAGE RECEPTION 4.1 Receive Message Buffering The MCP2515 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB) that acts as a third receive buffer (see Figure 4-2). 4.1.1 MESSAGE ASSEMBLY BUFFER Of the three receive buffers, the MAB is always committed to receiving the next message from the bus ...
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... MCP2515 interprets this as a SOF and a SOF pulse is generated. If the dominant condition does not remain until the sample point, the MCP2515 interprets this as a glitch on the bus and no SOF signal is generated. Figure 4-1 illustrates SOF signalling and glitch-filtering. ...
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... Acceptance Filter Acceptance Mask Acceptance Filter RXM0 Acceptance Filter Acceptance Filter RXF0 Acceptance Filter Acceptance Filter RXF1 M Identifier A B Data Field Preliminary MCP2515 CONFIGURING RXNBF PINS Pin Status Disabled, high-impedance X Receive buffer interrupt X Digital output = 0 0 Digital output = 1 1 RXM1 RXF2 RXF3 A c ...
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... MCP2515 FIGURE 4-3: RECEIVE FLOW FLOWCHART Determines if the receive register is empty and able to accept a new message CANINTF.RX0IF = ? Yes Generate Overflow Error: Move message into RXB0 1 Set CANINTF.RX0IF = Set RXB0CTRL.FILHIT <0> according to which filter criteria Yes 1 CANINTE.RX0IE = ? No Are 1 Yes BFPCTRL.B0BFM = and 1 BF1CTRL.B0BFE = ...
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... BUKT: Rollover Enable bit 1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full 0 = Rollover disabled bit 1 BUKT1: Read-only Copy of BUKT bit (used internally by the MCP2515) bit 0 FILHIT: Filter Hit bit - indicates which acceptance filter enabled reception of message 1 = Acceptance Filter 1 (RXF1 Acceptance Filter 0 (RXF0) ...
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... MCP2515 REGISTER 4-2: RXB1CTRL – RECEIVE BUFFER 1 CONTROL (ADDRESS: 70h) U-0 R/W-0 — RXM1 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-5 RXM: Receive Buffer Operating Mode bits 11 = Turn mask/filters off; receive any message 10 = Receive only valid messages with extended identifiers that meet filter criteria ...
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... Bit is cleared R-x R-x R-x R-x SID8 SID7 SID6 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R/W-0 R/W-0 R/W-0 B0BFE B1BFM B0BFM bit Bit is unknown R-x R-x R-x SID5 ...
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... MCP2515 REGISTER 4-5: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW (ADDRESS: 62h, 72h) R-x SID2 SID1 bit 7 bit 7-5 SID: Standard Identifier bits <2:0> These bits contain the three least significant bits of the Standard Identifier for the received message bit 4 SRR: Standard Frame Remote Transmit Request bit (valid only if IDE bit = ‘0’) ...
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... Bit is cleared R-x R-x R-x R-x RBnDm5 RBnDm4 RBnDm3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R-x R-x R-x EID2 EID1 EID0 bit Bit is unknown R-x R-x R-x DLC2 ...
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... If there is a match, that message will be loaded into the appropriate receive buffer. 4.5.1 DATA BYTE FILTERING When receiving standard data frames (11-bit identifier), the MCP2515 automatically applies 16 bits of masks and filters normally associated identifiers to the first 16 bits of the data field (data bytes 0 and 1) ...
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... This implies that RXB0 has a higher priority than RXB1. 4.5.5 CONFIGURING THE MASKS AND FILTERS The mask and filter registers can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). Acceptance Mask Register RXMn 0 RXMn ...
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... MCP2515 REGISTER 4-10: RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH (ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h) R/W-x R/W-x SID10 SID9 bit 7 bit 7-0 SID: Standard Identifier Filter bits <10:3> These bits hold the filter bits to be applied to bits <10:3> of the Standard Identifier portion of a ...
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... Bit is cleared R/W-0 R/W-0 R/W-0 R/W-0 SID8 SID7 SID6 SID5 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R/W-x R/W-x EID9 EID8 bit Bit is unknown R/W-x R/W-x EID1 EID0 bit Bit is unknown R/W-0 ...
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... MCP2515 REGISTER 4-15: RXMnSIDL – MASK n STANDARD IDENTIFIER LOW (ADDRESS: 21h, 25h) R/W-0 R/W-0 SID2 SID1 bit 7 bit 7-5 SID: Standard Identifier Mask bits <2:0> These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a received message bit 4-2 Unimplemented: Reads as ‘ ...
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... Digital Phase Lock Loop (DPLL) synchronization. The bit timing of the MCP2515 is implemented using a DPLL that is configured to synchronize to the incoming data, as well as provide the nominal timing for the transmitted data ...
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... MCP2515 PROPAGATION SEGMENT The Propagation Segment (PropSeg) exists to compensate for physical delays between nodes. The propagation delay is defined as twice the sum of the signal’s propagation time on the bus line, including the delays associated with the bus driver. The PropSeg is programmable from 1 – 8 TQ. ...
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... A transmitting node will not resynchronize on a positive phase error (e > 0 the absolute magnitude of the phase error is greater than the SJW, the appropriate phase segment will adjust by an amount equal to the SJW. Preliminary MCP2515 DS21801D-page 39 ...
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... MCP2515 FIGURE 5-3: SYNCHRONIZING THE BIT TIME Input Signal ( PropSeg SyncSeg SJW (PS1) Input Signal (e > 0) SyncSeg PropSeg SJW (PS1) Resynchronization to a Slower Transmitter (e > 0) Input Signal (e < 0) SyncSeg PropSeg SJW (PS1) Resynchronization to a Faster Transmitter (e < 0) DS21801D-page 40 PhaseSeg1 (PS1) Sample ...
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... Bit Timing Configuration Registers The configuration registers (CNF1, CNF2, CNF3) control the bit timing for the CAN bus interface. These registers can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). 5.5.1 CNF1 The BRP<5:0> bits control the baud rate prescaler. ...
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... MCP2515 REGISTER 5-1: CNF1 – CONFIGURATION 1 (ADDRESS: 2Ah) R/W-0 R/W-0 SJW1 SJW0 bit 7 bit 7-6 SJW: Synchronization Jump Width Length bits <1:0> Length = Length = Length = Length = bit 5-0 BRP: Baud Rate Prescaler bits <5:0> (BRP + 1)/F Q Legend Readable bit -n = Value at POR REGISTER 5-2: CNF2 – ...
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... R = Readable bit -n = Value at POR © 2005 Microchip Technology Inc. U-0 U-0 U-0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R/W-0 R/W-0 R/W-0 PHSEG22 PHSEG21 PHSEG20 bit Bit is unknown DS21801D-page 43 ...
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... MCP2515 NOTES: DS21801D-page 44 Preliminary © 2005 Microchip Technology Inc. ...
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... If this is not desired, the error interrupt service routine should address this. The Current Error mode of the MCP2515 can be read by the MCU via the EFLG register (see Register 6-3). Additionally, there is an error state warning flag bit ...
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... MCP2515 FIGURE 6-1: ERROR MODES STATE DIAGRAM REC < 127 or TEC < 127 Error-Passive REGISTER 6-1: TEC – TRANSMIT ERROR COUNTER (ADDRESS: 1Ch) R-0 TEC7 TEC6 bit 7 bit 7-0 TEC: Transmit Error Count bits <7:0> Legend Readable bit -n = Value at POR REGISTER 6-2: REC – RECEIVER ERROR COUNTER ...
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... R = Readable bit -n = Value at POR © 2005 Microchip Technology Inc. R-0 R-0 R-0 R-0 TXBO TXEP RXEP TXWAR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R-0 R-0 RXWAR EWARN bit Bit is unknown DS21801D-page 47 ...
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... MCP2515 NOTES: DS21801D-page 48 Preliminary © 2005 Microchip Technology Inc. ...
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... The CANINTF register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt can not be cleared if the respective condition still prevails ...
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... MCP2515 7.6.2 RECEIVER WARNING The REC has reached the MCU warning limit of 96. 7.6.3 TRANSMITTER WARNING The TEC has reached the MCU warning limit of 96. 7.6.4 RECEIVER ERROR-PASSIVE The REC has exceeded the error-passive limit of 127 and the device has gone to error-passive state. ...
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... R = Readable bit -n = Value at POR © 2005 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 ERRIF TX2IF TX1IF TX0IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R/W-0 R/W-0 RX1IF RX0IF bit Bit is unknown DS21801D-page 51 ...
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... MCP2515 NOTES: DS21801D-page 52 Preliminary © 2005 Microchip Technology Inc. ...
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... Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. A typical oscillator circuit is shown in Figure 8-1. The MCP2515 may also be driven by an external clock source connected to the OSC1 pin, as shown in Figure 8-2 and Figure 8-3. ...
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... MCP2515 FIGURE 8-3: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330 k 74AS04 0.1 mF Note 1: Duty cycle restrictions must be observed (see Table 12-2). TABLE 8-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq. OSC1 HS 8.0 MHz 27 pF 16.0 MHz 22 pF ...
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... RESET The MCP2515 differentiates between two resets: 1. Hardware Reset – Low on RESET pin. 2. SPI Reset – Reset via SPI command. Both of these resets are functionally equivalent important to provide one of these two resets after power-up to ensure that the logic and registers are in their default state ...
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... MCP2515 NOTES: DS21801D-page 56 Preliminary © 2005 Microchip Technology Inc. ...
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... Filter registers • Mask registers 10.2 Sleep Mode The MCP2515 has an internal Sleep mode that is used to minimize the current consumption of the device. The SPI interface remains active for reading even when the MCP2515 is in Sleep mode, allowing access to all registers. ...
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... Normal Mode Normal mode is the standard operating mode of the MCP2515. In this mode, the device actively monitors all bus messages and generates acknowledge bits, error frames, etc. This is also the only mode in which the MCP2515 will transmit messages over the CAN bus. ...
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... R = Readable bit -n = Value at POR © 2005 Microchip Technology Inc. R-0 R-0 U-0 R-0 — ICOD2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary MCP2515 R-0 R-0 U-0 ICOD1 ICOD0 — bit Bit is unknown DS21801D-page 59 ...
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... MCP2515 NOTES: DS21801D-page 60 Preliminary © 2005 Microchip Technology Inc. ...
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... REGISTER MAP The register map for the MCP2515 is shown in Table 11-1. Address locations for each register are determined by using the column (higher-order 4 bits) and row (lower-order 4 bits) values. The registers have been arranged to optimize the sequential TABLE 11-1: CAN CONTROLLER REGISTER MAP ...
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... MCP2515 NOTES: DS21801D-page 62 Preliminary © 2005 Microchip Technology Inc. ...
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... Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the MCP2515 (on the SO line) on the falling edge of SCK. The CS pin must be held low while any operation is performed. Table 12-1 shows the instruction bytes for all operations ...
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... DS21801D-page 64 The part is selected by lowering the CS pin and the Bit Modify command byte is then sent to the MCP2515. The command is followed by the address of the register, the mask byte and finally the data byte. The mask byte determines which bits in the register will be allowed to change. A ‘ ...
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... high-impedance Preliminary MCP2515 23 don’t care data out Address Points to Address 0 0 Receive Buffer 0, 0x61 Start at RXB0SIDH 0 1 Receive Buffer 0, 0x66 Start at RXB0D0 1 0 Receive Buffer 1, 0x71 Start at RXB1SIDH 1 1 Receive Buffer 1, 0x76 Start at RXB1D0 ...
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... MCP2515 FIGURE 12-5: LOAD TX BUFFER SCK instruction high-impedance SO FIGURE 12-6: REQUEST-TO-SEND (RTS) INSTRUCTION SCK FIGURE 12-7: BIT MODIFY INSTRUCTION SCK instruction Note: Not all registers can be accessed with this command. See the register map for a list of the registers that apply. DS21801D-page 66 ...
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... Msg Type Received 0 0 Standard data frame 0 1 Standard remote frame 1 0 Extended data frame 1 1 Extended remote frame The extended ID bit is mapped to bit 4. The RTR bit is mapped to bit 3. Preliminary MCP2515 23 repeat data out CANINTF.RX0IF CANINTFL.RX1IF TXB0CNTRL.TXREQ CANINTF.TX0IF TXB1CNTRL.TXREQ CANINTF.TX1IF TXB2CNTRL.TXREQ CANINTF ...
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... MCP2515 FIGURE 12-10: SPI™ INPUT TIMING CS 1 Mode 1,1 SCK Mode 0 MSB in SO FIGURE 12-11: SPI™ OUTPUT TIMING SCK 12 SO MSB out SI DS21801D-page high-impedance 13 don’t care Preliminary LSB in 2 Mode 1,1 Mode 0,0 14 LSB out © 2005 Microchip Technology Inc. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2005 Microchip Technology Inc. Preliminary MCP2515 +1.0V DD DS21801D-page 69 ...
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... MCP2515 TABLE 13-1: DC CHARACTERISTICS DC Characteristics Param. No. Sym Characteristic V Supply Voltage DD V Register Retention Voltage RET High-Level Input Voltage V RXCAN IH SCK, CS, SI, TXnRTS Pins OSC1 RESET Low-Level Input Voltage V RXCAN, TXnRTS Pins IL SCK, CS, SI OSC1 RESET Low-Level Output Voltage V TXCAN OL RXnBF Pins ...
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... AMB Min Max Units 100 — ns Industrial (I -40°C to +85°C AMB Extended (E -40°C to +125°C AMB Min Max Units 2 — µs Preliminary MCP2515 V = 2. 4.5V to 5.5V DD Conditions + T ) OSH OSL V = 2. 4.5V to 5.5V DD Conditions V = 2. ...
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... MCP2515 TABLE 13-5: CLKOUT PIN AC CHARACTERISTICS CLKOUT Pin AC/DC Characteristics Param. Sym Characteristic No. t CLKOUT Pin High Time h CLKOUT t CLKOUT Pin Low Time l CLKOUT t CLKOUT Pin Rise Time r CLKOUT t CLKOUT Pin Fall Time f CLKOUT t CLOCKOUT Propagation Delay d CLKOUT 15 t Start-Of-Frame High Time ...
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... AMB Extended (E -40°C to +125°C AMB Min Max Units — 10 MHz 50 — — — — — ns — 2 µs Note 1 — 2 µs Note 1 45 — — — — ns — — ns — 100 ns Preliminary MCP2515 V = 2. 4.5V to 5.5V DD Conditions DS21801D-page 73 ...
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... MCP2515 NOTES: DS21801D-page 74 Preliminary © 2005 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2005 Microchip Technology Inc. Example: MCP2515-I/P^^ 0434256 Example: MCP2515 E/SO^^ 0434256 Example: MCP2515 IST ^ 256 e 3 0434 Preliminary MCP2515 DS21801D-page 75 ...
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... MCP2515 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... L .016 .033 .050 .009 .011 .012 B .014 .017 .020 Preliminary MCP2515 A2 MILLIMETERS MIN NOM MAX 18 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 11.33 11.53 11.73 0.25 0.50 ...
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... MCP2515 20-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top ...
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... Changed supply voltage minimum to 2.7V. - Internal Capacitance: Changed V DD condition to 0V. - Standby Current (Sleep mode): Split specification into -40°C to +85°C and -40°C to +125°C. Revision A (May 2003) • Original Relase of this Document. © 2005 Microchip Technology Inc. within Preliminary MCP2515 DS21801D-page 79 ...
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... MCP2515 NOTES: DS21801D-page 80 Preliminary © 2005 Microchip Technology Inc. ...
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... Plastic SOIC (300 mil Body), 18-Lead ST = TSSOP, (4.4 mm Body), 20-Lead © 2005 Microchip Technology Inc. Examples: a) MCP2515-E/P: b) MCP2515-I/P: c) MCP2515-E/SO: Extended Temperature, d) MCP2515-I/SO: Industrial Temperature, e) MCP2515T-I/SO: Tape and Reel, f) MCP2515-I/ST: Industrial Temperature, g) MCP2515T-I/ST: Tape and Reel, Preliminary MCP2515 . Extended Temperature, 18LD PDIP package. Industrial Temperature, 18LD PDIP package ...
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... MCP2515 NOTES: DS21801D-page 82 Preliminary © 2005 Microchip Technology Inc. ...
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... Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. © 2005 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Preliminary © 2005 Microchip Technology Inc. EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 ...