PIC16F73-I/SP Microchip Technology Inc., PIC16F73-I/SP Datasheet - Page 102

• Manufacturer Part Number: PIC16F73-I/SP
• Description: 28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F73-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
12.11.1
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 12.14 for details on SLEEP mode.
12.11.2
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>). (Section 5.0)
12.11.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>), see
Section 4.2.
EXAMPLE 12-1:
DS30325B-page 100
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
on
INT INTERRUPT
TMR0 INTERRUPT
PORTB INTCON CHANGE
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
the
by
RB0/INT
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
setting/clearing
pin,
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Insert user code here
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
flag
enable
bit
INTF
bit
12.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W, PCLATH and STA-
TUS registers). This will have to be implemented in
software, as shown in Example 12-1.
For the PIC16F73/74 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 20h in bank 0, it must
also be defined at A0h in bank 1.). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F76/77 devices, temporary holding registers
W_TEMP,
should be placed in here. These 16 locations don’t
require banking and, therefore, make it easier for con-
text save and restore. The same code shown in
Example 12-1 can be used.
STATUS_TEMP
 2002 Microchip Technology Inc.
and
PCLATH_TEMP