DSPIC33FJ256GP710-I/PF Microchip Technology Inc., DSPIC33FJ256GP710-I/PF Datasheet - Page 176
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DSPIC33FJ256GP710-I/PF
Manufacturer Part Number
DSPIC33FJ256GP710-I/PF
Description
16 BIT MCU/DSP 100LD 40MIPS 256KB FLASH
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC33FJ256GP710-IPF.pdf
(371 pages)
Specifications of DSPIC33FJ256GP710-I/PF
A/d Inputs
32-Channels, 12-Bit
Comparators
8
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART
Ios
85
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Ram Size
30K Bytes
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6
Lead Free Status / Rohs Status
RoHS Compliant part
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dsPIC33F
14.4
REGISTER 14-1:
DS70165D-page 174
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-5
bit 4
bit 3
bit 2-0
Note 1:
U-0
U-0
—
—
Output Compare Register
Refer to the device data sheet for specific time bases available to the output compare module.
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1 = Output Compare x will halt in CPU Idle mode
0 = Output Compare x will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)
OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for Compare x
0 = Timer2 is the clock source for Compare x
OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx, Fault pin enabled
110 = PWM mode on OCx, Fault pin disabled
101 = Initialize OCx pin low, generate continuous output pulses on OCx pin
100 = Initialize OCx pin low, generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high, compare event forces OCx pin low
001 = Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
U-0
U-0
—
—
OCxCON: OUTPUT COMPARE x CONTROL REGISTER
HC = Cleared in Hardware
W = Writable bit
‘1’ = Bit is set
OCSIDL
R/W-0
U-0
—
R-0 HC
OCFLT
Preliminary
U-0
—
(1)
HS = Set in Hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OCTSEL
R/W-0
U-0
—
(1)
R/W-0
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
OCM<2:0>
R/W-0
U-0
—
R/W-0
U-0
—
bit 8
bit 0
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