74HC193N Philips Semiconductors, 74HC193N Datasheet

74HC193N

Manufacturer Part Number

74HC193N

Description

4-BIT BINARY UP/DOWN COUNTER

Manufacturer

Philips Semiconductors

Datasheet

1.74HC193N.pdf (9 pages)

Specifications of 74HC193N

Circuit Type

High Speed, Low-Power Schottky, Silicon Gate

Current, Supply

160 μA

Function Type

4-Bits

Logic Function

Counter

Logic Type

CMOS

Package Type

DIP-16

Special Features

Binary

Temperature, Operating, Range

-40 to +125 °C

Voltage, Supply

5 V

Lead Free Status / Rohs Status

RoHS Compliant part Electrostatic Device

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1. General description

The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin

compatible with Low power Schottky TTL (LSTTL). They are speciﬁed in compliance with

JEDEC standard no. 7A.

The 74HC193 and 74HCT193 are 4-bit synchronous binary up/down counters. Separate

up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state

synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is

pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while

CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at

any time, or erroneous operation will result. The device can be cleared at any time by the

asynchronous master reset input (MR); it may also be loaded in parallel by activating the

asynchronous parallel load input (PL).

The 74HC193 and 74HCT193 each contain four master-slave JK ﬂip-ﬂops with the

necessary steering logic to provide the asynchronous reset, load, and synchronous count

up and count down functions.

Each ﬂip-ﬂop contains JK feedback from slave to master, such that a LOW-to-HIGH

transition on the CPD input will decrease the count by one, while a similar transition on the

CPU input will advance the count by one.

One clock should be held HIGH while counting with the other, otherwise the circuit will

either count by twos or not at all, depending on the state of the ﬁrst ﬂip-ﬂop, which cannot

toggle as long as either clock input is LOW. Applications requiring reversible operation

must make the reversing decision while the activating clock is HIGH to avoid erroneous

counts.

The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH.

When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW

transition of CPU will cause TCU to go LOW.

TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock.

Likewise, the TCD output will go LOW when the circuit is in the zero state and the

CPD goes LOW. The terminal count outputs can be used as the clock input signals to the

next higher order circuit in a multistage counter, since they duplicate the clock waveforms.

Multistage counters will not be fully synchronous, since there is a slight delay time

difference added for each stage that is added.

The counter may be preset by the asynchronous parallel load capability of the circuit.

Information present on the parallel data inputs (D0 to D3) is loaded into the counter and

appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when

the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will

disable the parallel load gates, override both clock inputs and set all outputs (Q0 to

74HC193; 74HCT193

Presettable synchronous 4-bit binary up/down counter

Product data sheet

Related parts for 74HC193N

74HC193N Summary of contents

Page 1

Presettable synchronous 4-bit binary up/down counter 1. General description The 74HC193 and 74HCT193 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC standard no. 7A. ...

Page 2

... Synchronous reversible 4-bit binary counting I Asynchronous parallel load I Asynchronous reset I Expandable without external logic 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC193D +125 C 74HC193DB +125 C 74HC193N +125 C 74HC193PW +125 C 74HCT193D +125 C 74HCT193DB +125 C 74HCT193N +125 C 74HCT193PW +125 C 4. Functional diagram ...

Page 3

NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK I ...

Page 4

NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter 74HCT193 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t rise time r t fall time f 9. Static characteristics Table 6. Static ...

Page 5

NXP Semiconductors Table 6. Static characteristics type 74HC193 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input ...

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74HC193N Philips Semiconductors, 74HC193N Datasheet

74HC193N

Specifications of 74HC193N

Available stocks

Related parts for 74HC193N

74HC193N Summary of contents

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