TJA1020T/N1,118 NXP Semiconductors, TJA1020T/N1,118 Datasheet - Page 7
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TJA1020T/N1,118
Manufacturer Part Number
TJA1020T/N1,118
Description
IC TXRX CAN 8BIT 27V 8SOIC
Manufacturer
NXP Semiconductors
Type
Transceiverr
Datasheet
1.TJA1020TN1112.pdf
(22 pages)
Specifications of TJA1020T/N1,118
Package / Case
8-SOIC (3.9mm Width)
Number Of Drivers/receivers
1/1
Protocol
LIN
Voltage - Supply
5 V ~ 27 V
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5050-2
935268733118
TJA1020T/N1,118
TJA1020TD-T
TJA1020TD-T
935268733118
TJA1020T/N1,118
TJA1020TD-T
TJA1020TD-T
Philips Semiconductors
Wake-up via mode transition
It is also possible to set pin INH HIGH with a mode
transition towards normal slope/low slope mode via
pin NSLP. This is useful for applications with a
continuously powered microcontroller.
Wake-up source recognition
The TJA1020 can distinguish between a local wake-up
request on pin NWAKE and a remote wake-up request via
a dominant bus state. The wake-up source flag is set in
case the wake-up request was a local one. The wake-up
source can be read on pin TXD in the standby mode. If an
external pull-up resistor on pin TXD to the power supply
voltage of the microcontroller has been added a HIGH
level indicates a remote wake-up request (weak pull-down
at pin TXD) and a LOW level indicates a local wake-up
request (strong pull-down at pin TXD; much stronger than
the external pull-up resistor).
The wake-up request flag (signalled on pin RXD) as well
as the wake-up source flag (signalled on pin TXD) are
reset immediately, if the microcontroller sets pin NSLP
HIGH.
TXD dominant time-out function
A ‘TXD Dominant Time-out’ timer circuit prevents the bus
line from being driven to a permanent dominant state
(blocking all network communication) if pin TXD is forced
permanently LOW by a hardware and/or software
application failure. The timer is triggered by a negative
edge on pin TXD. If the duration of the LOW level on
2004 Jan 13
handbook, full pagewidth
LIN transceiver
V LIN
LIN dominant
0.4V BAT
sleep mode
LIN recessive
Fig.4 Wake-up behaviour.
t BUS
7
pin TXD exceeds the internal timer value (t
transmitter is disabled, driving the bus line into a recessive
state. The timer is reset by a positive edge on pin TXD.
Fail-safe features
Pin TXD provides a pull-down to GND in order to force a
predefined level on input pin TXD in case the pin TXD is
unsupplied.
Pin NSLP provides a pull-down to GND in order to force
the transceiver into sleep mode in case the pin NSLP is
unsupplied.
Pin RXD is set floating in case of lost power supply on pin
BAT.
The current of the transmitter output stage is limited in
order to protect the transmitter against short-circuit to pins
BAT or GND.
A loss of power (pins BAT and GND) has no impact to the
bus line and the microcontroller. There are no reverse
currents from the bus. The LIN transceiver can be
disconnected from the power supply without influencing
the LIN bus.
The output driver at pin LIN is protected against
overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature T
thermal protection circuit disables the output driver. The
driver is enabled again if the junction temperature has
been decreased below T
present at pin TXD.
standby mode
j(sd)
V BAT
0.6V BAT
ground
MBL371
and a recessive level is
Product specification
TJA1020
dom
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