PIC10F206-I/P Microchip Technology Inc., PIC10F206-I/P Datasheet - Page 27

• Manufacturer Part Number: PIC10F206-I/P
• Description: 8 PIN, 768 B FLASH, 24 RAM, 4 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC10F206-I/P

• Comparators: 1
• Cpu Speed: 1 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 4 MHz
• Input Output: 4
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 750 Bytes
• Ram Size: 24 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.0
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimple-
mented and read as ‘0’s. Please note that GP3 is an
input-only pin. Pins GP0, GP1 and GP3 can be config-
ured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin selectable. If GP3/MCLR is config-
ured as MCLR, weak pull-up is always on and wake-up
on change for this pin is not enabled.
5.2
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are GP3, which is input-only and the GP2/T0CKI/
COUT/FOSC4 pin, which may be controlled by various
registers. See Table 5-1.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
TABLE 5-1:
© 2006 Microchip Technology Inc.
Priority
Note:
1
2
3
4
I/O PORT
GPIO
TRIS Registers
TRIS GPIO
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
CIN+
GP0
—
—
ORDER OF PRECEDENCE
FOR PIN FUNCTIONS
TRIS GPIO
CIN-
GP1
—
—
TRIS GPIO
FOSC4
COUT
T0CKI
GP2
I/MCLR
GP3
—
—
—
Preliminary
PIC10F200/202/204/206
5.3
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input-
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1:
Data
Bus
WR
Port
W
Reg
TRIS ‘f’
Note 1: See Table 3-2 for buffer type.
I/O Interfacing
D
D
CK
CK
TRIS
Latch
Data
Latch
Reset
Q
Q
Q
Q
PIC10F200/202/204/206
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
RD Port
(1)
V
V
P
N
DS41239C-page 25
SS
DD
V
V
DD
SS
I/O
pin