DS26521L+ Maxim Integrated Products, DS26521L+ Datasheet
DS26521L+
Specifications of DS26521L+
Related parts for DS26521L+
DS26521L+ Summary of contents
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GENERAL DESCRIPTION The DS26521 is a single-channel framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each channel configurable, supporting both long-haul and short-haul lines. APPLICATIONS Routers Channel Service Units (CSUs) Data Service Units (DSUs) ...
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DETAILED DESCRIPTION ...............................................................................................9 1 AJOR PERATING ODES 2. FEATURE HIGHLIGHTS ................................................................................................10 2.1 G ......................................................................................................................................10 ENERAL 2 ............................................................................................................................10 INE NTERFACE 2 ....................................................................................................................10 LOCK YNTHESIZER 2 .....................................................................................................................10 ITTER TTENUATOR 2 ...
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E1 Automatic Alarm Generation .......................................................................................................... 54 8.9.9 Error-Count Registers .......................................................................................................................... 55 8.9.10 DS0 Monitoring Function...................................................................................................................... 57 8.9.11 Transmit Per-Channel Idle Code Insertion........................................................................................... 58 8.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 58 8.9.13 Per-Channel Loopback ........................................................................................................................ 58 8.9.14 E1 G.706 Intermediate ...
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JTAG BOUNDARY SCAN AND TEST ACCESS PORT ..............................................250 13.1 TAP C S ONTROLLER 13.1.1 Test-Logic-Reset................................................................................................................................ 251 13.1.2 Run-Test-Idle ..................................................................................................................................... 251 13.1.3 Select-DR-Scan ................................................................................................................................. 251 13.1.4 Capture-DR ........................................................................................................................................ 251 13.1.5 Shift-DR.............................................................................................................................................. 251 13.1.6 Exit1-DR............................................................................................................................................. 251 13.1.7 Pause-DR........................................................................................................................................... 251 13.1.8 Exit2-DR............................................................................................................................................. ...
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Figure 6-1. Block Diagram ......................................................................................................................................... 17 Figure 6-2. Detailed Block Diagram........................................................................................................................... 18 Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0).............................................. 26 Figure 8-2. SPI Serial Port Access for Read Mode (SPI_CPOL = 1, ...
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Figure 12-7. Receive-Side Timing, Elastic Store Enabled (T1 Mode)..................................................................... 244 Figure 12-8. Receive Framer Timing—Line Side .................................................................................................... 244 Figure 12-9. Transmit Formatter Timing—Backplane ............................................................................................. 246 Figure 12-10. Transmit Formatter Timing, Elastic Store Enabled ........................................................................... 247 Figure 12-11. Transmit Formatter Timing—Line ...
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Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 19 Table 8-1. Reset Functions........................................................................................................................................ 29 Table 8-2. Registers Related to the Elastic ...
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Table 9-18. Receive Impedance Selection.............................................................................................................. 210 Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 211 Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 211 Table 9-21. BERT Register Set ............................................................................................................................... 212 Table 9-22. BERT Pattern Select ............................................................................................................................ ...
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DETAILED DESCRIPTION The DS26521 is a single-channel device that can be software configured for T1, E1 operation. The DS26521 is composed of a line interface unit (LIU), framer, HDLC controller, and a TDM backplane interface, and is ...
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FEATURE HIGHLIGHTS 2.1 General Single-port member of the TEX-series transceiver family of devices Software compatible with the DS26522 dual, DS26524 quad, and DS26528 octal transceivers 64-pin LQFP package 3.3V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG ...
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Detailed alarm and status reporting with optional interrupt support Large path and line error counters − T1: BPV, CV, CRC-6, and framing bit errors − E1: BPV, CV, CRC-4, E-bit, and frame alignment errors − Timed or manual update modes ...
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HDLC Controllers One HDLC controller engine for each T1/E1 port Independent 64-byte Rx and Tx buffers with interrupt support Access FDL, Sa, or single DS0 channel Compatible with polled or interrupt driven environments 2.8 Test and Diagnostics IEEE 1149.1 ...
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APPLICATIONS The DS26521 is useful in applications such as: Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment DS26521 Single T1/E1/J1 Transceiver 13 of 258 ...
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SPECIFICATIONS COMPLIANCE The DS26521 LIU meets all the latest relevant telecommunications specifications. the T1 and E1 specifications and relevant sections that are applicable to the DS26521. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface AMI Coding ...
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Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to- peak space voltage is ±0.237V; nominal pulse width is ...
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ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit assumed that the framing bit is ...
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BLOCK DIAGRAMS Figure 6-1. Block Diagram DS26521 RTIP RRING LINE INTERFACE TTIP UNIT TRING MICRO PROCESSOR INTERFACE CONTROLLER PORT DS26521 Single T1/E1/J1 Transceiver T1/E1 FRAMER BACKPLANE INTERFACE HDLC ELASTIC BERT STORES CLOCK JTAG PORT GENERATION TEST CLOCK PORT ADAPTER ...
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Figure 6-2. Detailed Block Diagram TRANSMIT TTIP LIU Waveform Shaper/Line TRING Driver RECEIVE RTIP LIU Clock/Data RRING Recovery DS26521 MICROPROCESSOR INTERF ACE Serial Interface Mode: (SCLK, CPOL, CPHA, SPI SWAP, MOSI, and MISO) DS26522 Tx BERT HDLC Tx FRAMER: B8ZS/ ...
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PIN DESCRIPTIONS 7.1 Pin Functional Description Table 7-1. Detailed Pin Descriptions NAME PIN TYPE Analog Output, TTIP 6 High Impedance Analog Output, TRING 7 High Impedance TXENABLE 13 Analog RTIP 10 Input Analog RRING 11 Input TSER 64 TCLK ...
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NAME PIN TYPE TSYNC 61 I/O TSSYNCIO 60 I/O I TSIG 59 TCHBLK CLK FUNCTION Transmit Synchronization. A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. This signal can also be programmed ...
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NAME PIN TYPE O RSER 57 O RCLK 56 RSYSCLK 55 I I/O RSYNC 54 RMSYNC RFSYNC O RSIG 52 AL/ RSIGF FLOS RLF LTC FUNCTION RECEIVE FRAMER Received Serial Data. Received NRZ serial ...
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NAME PIN TYPE RCHBLK CLK BPCLK 48 O A12 D[7 SPI_CPOL D[6 SPI_CPHA D[5]/ ...
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NAME PIN TYPE D[2 SPI_SCLK D[1 SPI_MOSI D[0 SPI_MISO CSB 34 I RDB / 35 I DSB WRB / 36 I RWB SPI_SEL 1 I INTB 37 U BTS 2 I MCLK 39 I ...
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NAME PIN TYPE JTRST 47 I, Pullup JTMS 46 I, Pullup JTCLK 45 JTDI 44 I, Pullup O, High JTDO 43 impedance SCANMODE 3 SCAN_EN 4 ATVDD 5 — ATVSS 8 — ARVDD 9 — ARVSS 12 — ACVDD 40 ...
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FUNCTIONAL DESCRIPTION 8.1 Microprocessor Interface 8.1.1 Parallel Port Mode Parallel port control of the DS26521 is accomplished through the 26 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes ...
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SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing. Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0) SPI_SCLK CSB SPI_MOSI 1 A13 ...
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Figure 8-5. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 0) SPI_SLCK CSB 0 A13 A12 A11 A10 SPI_MOSI MSB SPI_MISO Figure 8-6. SPI Serial Port Access for Write Mode (SPI_CPOL = 1, SPI_CPHA = 0) ...
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Clock Structure The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz multiple the T1 and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy. ...
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Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. ...
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Initialization and Configuration 8.4.1 Example Device Initialization Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device using the software reset bits outlined in Section 8.3. Clear all reset bits. ...
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Figure 8-10. Device Interrupt Information Flow Diagram Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss of Signal Clear Receive Loss of Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss of Signal Receive Loss of ...
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System Backplane Interface The DS26521 provides a versatile backplane interface that can be configured to the following: • Transmit and receive two-frame elastic stores • Mapping of T1 channels into a 2.048MHz backplane • IBO mode for multiple framers ...
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Elastic Stores Initialization There are two elastic store initializations that can be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write ...
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Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit (TIOCR.4) enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode the user can choose which of the backplane channels ...
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Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit (RIOCR.4) to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can ...
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H.100 (CT Bus) Compatibility The registers used for controlling the H.100 backplane are The H.100 (or CT bus synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, ...
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Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode 1 TSSYNCIO 2 TSSYNCIO TSYSCLK TSER BIT 8 NOTE 1: TSSYNCIO IN NORMAL OPERATION. NOTE 2: TSSYNCIO WITH H.100EN = 1 and TSSYNCINV = 1. NOTE 3: t (BIT ...
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Framers The DS26521 framer core is software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms also used for extracting and inserting signaling data, ...
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Table 8-6. ESF Framing Mode FRAME FRAMING NUMBER Table 8-7. SLC-96 ...
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FRAME NUMBER ...
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E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 8-8. E1 FAS/NFAS Framing CRC-4 FRAME TYPE FAS C1 1 NFAS 0 2 FAS C2 3 NFAS 0 4 FAS C3 5 ...
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Table 8-9 shows registers that are related to setting up the framing. Table 8-9. Registers Related to Setting Up the Framer REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register 1 (TCR1) Transmit Control Register 2 (TCR2) Transmit Control Register ...
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T1 Transmit Synchronizer The DS26521 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer ...
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Signaling The DS26521 supports both software- and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26521 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss, or change of frame alignment. The ...
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Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor based refers to access through the transmit-signaling registers, TS1:TS16, while hardware based refers to using the TSIG pins. ...
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Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling registers, RS1:RS16. Hardware based refers to the ...
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Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment mode, this action meets ...
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Receive SLC-96 Operation (T1 Mode Only SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is ...
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Receive Bit-Oriented Code (BOC) Controller The DS26521 framer contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1, ESF mode in the data link bits. ...
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The Transmit FDL register (T1TFDL) contains the facility data link (FDL) information that inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first mode, only the lower six bits ...
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Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26521, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal an ...
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Table 8-18 shows some of the registers related to maintenance and alarms. Table 8-18. Registers Related to Maintenance and Alarms REGISTER Receive Real-Time Status Register 1 (RRTS1) Receive Interrupt Mask Register 1(RIM1) Receive Latched Status Register 2 (RLS2) Receive Real-Time ...
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Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. Status bits can operate in either a latched or real-time fashion. Some latched ...
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Table 8-19. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 (Note: This mode is RAI also referred to as the (Yellow “Japanese ...
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RAI- repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of “00000000 11111111” (right-to-left ) with 90ms of “00111110 11111111.” The RRAI-CI bit is set when a ...
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Table 8-21. E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT (ERCNT. 8.9.9.2 Path Code Violation Count Register (PCVCR operation, the Path Code Violation Count register (PCVCR) records either Ft, Fs, or CRC-6 errors. When ...
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E-Bit Counter (EBCR) This counter is only available in E1 mode. E-Bit Count Register 1 (E1EBCR1) is the most significant word and E-Bit Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end ...
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Transmit Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition registers (TIDR1:TIDR32) are provided to set the 8-bit idle code ...
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T1 Programmable In-Band Loop Code Generator The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-25. Registers Related to ...
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T1 Programmable In-Band Loop Code Detection The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-26. Registers Related to ...
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Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by Receive Control Register 3 (RCR3). Table 8-27. Registers Related to Framer Payload Loopbacks RECEIVE CONTROL FRAMER REGISTER 3 (RCR3) ADDRESSES Framer Loopback Payload Loopback Remote Loopback 083h ...
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HDLC Controllers 8.10.1 Receive HDLC Controller The DS26521 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has a ...
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HDLC FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO. When the receive ...
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Figure 8-15. Receive HDLC Example Start New Start New Message Buffer Message Buffer Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Start New Message Buffer Message Buffer Enable Interrupts RPE and RHWM NO Interrupt? ...
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Transmit HDLC Controller 8.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many ...
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Figure 8-16. HDLC Message Transmit Example Loop Action Required Work Another Process Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Read TFBA N = TFBA[6..0] Push Message Byte ...
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Line Interface Units (LIUs) The DS26521 combines an LIU transmit and receive front-end with its framers. The LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data recovery; and ...
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Figure 8-17. Basic Balanced Network Connections F1 TX TIP RING TIP RING F4 NAME 1.25A Slow Blow Fuse 1.25A Slow Blow Fuse S1, S2 25V (max) ...
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Table 8-29. Recommended Supply Decoupling SUPPLY PINS CAPACITANCE DVDD/DVSS 0.1μF + 0.1μF + 1μF + 10μF DVDDIO/DVSSIO 0.1μF + 0.1μF + 1μF + 10μF ATVDD/ATVSS (0.1μF + 1μF + 10μ ARVDD/ARVSS (0.1μF + 1μF + 10μ ...
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Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator enabled for the transmit path. A digital sequencer and DAC ...
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Transmit-Line Pulse Shapes The DS26521 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in shape can be configured for each LIU on an individual basis. The ...
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Figure 8-19. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 8.11.2.2 Transmit Power-Down The individual transmitters can be powered down by setting the TPDE bit in the LIU ...
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Receiver The DS26521 contains identical receivers. Both receivers are designed to be fully software-selectable for E1, T1, and J1 without the need to change any external resistors. The device couples to the receive twisted pair (or ...
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Figure 8-20. Typical Monitor Application T1/E1 LINE Rm 8.11.3.4 Loss of Signal (LOS) The DS26521 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775, or ETS 300 233 for ...
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ANSI T1.231 for T1 and J1 Modes For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity ...
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Jitter Attenuator The DS26521 contains a jitter attenuator for each LIU that can be set to a depth 128 bits via the JADS (LTRCR.4) bit in the LIU Transmit Receive Control register (LTRCR). The 128-bit mode ...
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LIU Loopbacks The DS26521 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote loopback, and dual loopback. In the loopback diagrams that follow, TSER, TCLK, RSER, and RCLK are inputs/outputs from the framer. 8.11.5.1 Analog Loopback ...
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Remote Loopback The outputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are ignored during a remote loopback. This loopback is conceptually shown in Figure 8-24. Remote Loopback TCLK ...
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Bit-Error-Rate Test (BERT) Function The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers. Table 8-35 ...
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The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS • A repetitive pattern from bits in length • Alternating (16-bit) words that flip every 1 to ...
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DEVICE REGISTERS Thirteen address bits are used to control the settings of the registers. The address map is compatible with the Dallas Semiconductor dual framer product, DS26522. The registers control functions of the framers, LIU, and BERT within the ...
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Global Register List Table 9-2. Global Register List ADDRESS NAME 0F0h GTCR1 0F1h GFCR 0F2h GTCR2 0F3h GTCCR 0F4h — 0F5h GLSRR 0F6h GFSRR 0F7h — 0F8h IDR 0F9h GFISR 0FAh GBISR 0FBh GLISR 0FCh GFIMR 0FDh GBIMR 0FEh ...
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Framer Register List Table 9-3. Framer Register List ADDRESS NAME 000h–00Fh — 010h RHC 011h RHBSE 012h RDS0SEL 013h RSIGC T1RCR2 014h E1RSAIMR 015h T1RBOCC 016h–01Fh — 020h RIDR1 021h RIDR2 022h RIDR3 023h RIDR4 024h RIDR5 025h RIDR6 ...
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ADDRESS NAME 041h RS2 042h RS3 043h RS4 044h RS5 045h RS6 046h RS7 047h RS8 048h RS9 049h RS10 04Ah RS11 04Bh RS12 04Ch RS13 04Dh RS14 04Eh RS15 04Fh RS16 050h LCVCR1 051h LCVCR2 052h PCVCR1 053h PCVCR2 ...
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ADDRESS NAME 085h RESCR 086h ERCNT 087h RHFC 088h RIBOC 089h T1RSCC 08Ah RXPC 08B RBPBS 08Ch–08Fh — 090h RLS1 091h RLS2 092h RLS3 093 RLS4 094h RLS5 095h — RLS7 096h RLS7 097h — 098h RSS1 099h RSS2 09Ah ...
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ADDRESS NAME 0C1h RBCS2 0C2h RBCS3 0C3h RBCS4 0C4h RCBR1 0C5h RCBR2 0C6h RCBR3 0C7h RCBR4 0C8h RSI1 0C9h RSI2 0CAh RSI3 0CBh RSI4 0CCh RGCCS1 0CDh RGCCS2 0CEh RGCCS3 0CFh RGCCS4 0D0h RCICE1 0D1h RCICE2 0D2h RCICE3 0D3h RCICE4 ...
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ADDRESS NAME 12Dh TIDR14 12Eh TIDR15 12Fh TIDR16 130h TIDR17 131h TIDR18 132h TIDR19 133h TIDR20 134h TIDR21 135h TIDR22 136h TIDR23 137h TIDR24 138h TIDR25 139h TIDR26 13Ah TIDR27 13Bh TIDR28 13Ch TIDR29 13Dh TIDR30 13Eh TIDR31 13Fh TIDR32 ...
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ADDRESS NAME 16Bh E1TSa6 16Ch E1TSa7 16Dh E1RSa8 16Eh–17Fh — 180h TMMR TCR1 181h TCR1 TCR2 182h TCR2 183h TCR3 184h TIOCR 185h TESCR 186h TCR4 187h THFC 188h TIBOC 189h TDS0SEL 18Ah TXPC 18Bh TBPBS 18Ch–18Dh — 18Eh TSYNCC ...
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ADDRESS NAME 1CCh TGCCS1 1CDh TGCCS2 1CEh TGCCS3 1CFh TGCCS4 1D0h PCL1 1D1h PCL2 1D2h PCL3 1D3h PCL4 1D4h TBPCS1 1D5h TBPCS2 1D6h TBPCS3 1D7h TBPCS4 1D8h–1FFh — FRAMER REGISTER LIST DESCRIPTION Only) Transmit Gapped-Clock Channel Select Register 1 Transmit ...
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LIU and BERT Register List Table 9-4. LIU Register List ADDRESS NAME 1000h LTRCR LIU Transmit Receive Control Register 1001h LTITSR LIU Transmit Impedance and Pulse Shape Selection Register 1002h LMCR LIU Maintenance Control Register 1003h LRSR LIU Real ...
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Register Bit Maps 9.2.1 Global Register Bit Map Table 9-6. Global Register Bit Map ADDR NAME BIT 7 0F0h GTCR1 — 0F1h GFCR — 0F2h GTCR2 — 0F3h GTCCR BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 0F4h — — 0F5h GLSRR — ...
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Framer Register Bit Map Table 9-7 contains the framer registers of the DS26521. Some registers have dual functionality based on the selection of T1/ operating mode in the shown below using two lines of text. The first ...
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ADDR NAME BIT 7 — 03Bh RIDR28 C7 T1RDMWE1 CH8 03Ch RIDR29 C7 T1RDMWE2 CH16 03Dh RIDR30 C7 T1RDMWE3 CH24 03Eh RIDR31 C7 03Fh RIDR32 C7 CH1-A 040h RS1 0 CH2-A 041h RS2 CH1-A CH3-A 042h RS3 CH2-A CH4-A 043h ...
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ADDR NAME BIT 7 056h E1EBCR1 EB15 057h E1EBCR2 EB7 060h RDS0M B1 061h — — T1RFDL RFDL7 062h E1RRTS7 CSC5 063h T1RBOC — T1RSLC1 C8 064h E1RAF Si T1RSLC2 M2 065h E1RNAF Si T1RSLC3 S=1 066h E1RSiAF SiF14 067h ...
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ADDR NAME BIT 7 097h — — 098h RSS1 CH8 099h RSS2 CH16 09Ah RSS3 CH24 — 09Bh RSS4 CH32 C7 09Ch T1RSCD1 — C7 09Dh T1RSCD2 — 09Fh RIIR — 0A0h RIM1 RRAIC — 0A1h RIM2 — RIM3 (T1) ...
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ADDR NAME BIT 7 0C9h RSI2 CH16 0CAh RSI3 CH24 — 0CBh RSI4 CH32 0CCh RGCCS1 CH8 0CDh RGCCS2 CH16 0CEh RGCCS3 CH24 — 0CFh RGCCS4 CH32 0D0h RCICE1 CH8 0D1h RCICE2 CH16 0D2h RCICE3 CH24 — 0D3h RCICE4 CH32 ...
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ADDR NAME BIT 7 135h TIDR22 C7 136h TIDR23 C7 137h TIDR24 C7 — 138h TIDR25 C7 — 139h TIDR26 C7 — 13Ah TIDR27 C7 — 13Bh TIDR28 C7 — 13Ch TIDR29 C7 — 13Dh TIDR30 C7 — 13Eh TIDR31 ...
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ADDR NAME BIT 7 — 14Eh TS15 CH14-A — 14Fh TS16 CH15-A 150h TCICE1 CH8 151h TCICE2 CH16 152h TCICE3 CH24 — 153h TCICE4 CH32 TFDL7 162h T1TFDL — — 163h T1TBOC — T1TSLC1 C8 164h E1TAF Si T1TSLC2 M2 ...
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ADDR NAME BIT 7 18Ah TXPC — 18Bh TBPBS BPBSE8 — 18Eh TSYNCC — TESF 190h TLS1 TESF — 191h TLS2 — 192h TLS3 — 19Fh TIIR — TESF 1A0h TIM1 TESF — 1A1h TIM2 — 1A2h TIM3 — C7 ...
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ADDR NAME BIT 7 1D4h TBPCS1 CH8 1D5h TBPCS2 CH16 1D6h TBPCS3 CH24 — 1D7h TBPCS4 CH32 *RLS6 is reserved for future use. **Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. 9.2.3 ...
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Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit descriptions are presented in this section. ...
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Register Name GTCR1 Register Description: Global Transceiver Control Register 1 Register Address: 0F0h Bit # 7 6 Name — — Default 0 0 Bit 5: Receive Loss of Frame/Loss of Transmit Clock Indication Select (RLOFLTS RLOF/LTC pin indicates ...
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Register Name: GFCR Description: Global Framer Control Register Register Address: 0F1h Bit # 7 6 Name — — Default 0 0 Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on ...
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Register Name: GTCCR Register Description: Global Transceiver Clock Control Register Register Address: 0F3h Read/Write Function R/W Bit # 7 6 Name BPREFSEL3 BPREFSEL2 Default 0 0 Bits Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock ...
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Register Name: GLSRR Register Description: Global LIU Software Reset Register Register Address: 0F5h Bit # 7 6 Name — — Default 0 0 Bit 0: LIU Software Reset (LSRST1). LIU logic and registers are reset with a 0-to-1 transition in ...
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Register Name: IDR Register Description: Device Identification Register Register Address: 0F8h Bit # 7 6 Name ID7 ID6 Default 0 1 Bits Device ID (ID[7:3]). The upper five bits of the IDR are used to display the ...
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Register Name: GFISR Register Description: Global Framer Interrupt Status Register Register Address: 0F9h Bit # 7 6 Name — — Default 0 0 The GFISR register reports the framer interrupt status for the T1/E1 framer. A logic one indicates the ...
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Register Name: GFIMR Register Description: Global Framer Interrupt Mask Register Register Address: 0FCh Bit # 7 6 Name — — Default 0 0 Bit 0: Framer 1 Interrupt Mask (FIM1 Interrupt masked Interrupt enabled. Register Name: ...
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Framer Register Definitions See Table 9-3 for the complete framer register list. 9.4.1 Receive Register Definitions Register Name: RHC Register Description: Receive HDLC Control Register Register Address: 010h Bit # 7 6 Name RCRCD RHR Default 0 0 Bit ...
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Register Name: RHBSE Register Description: Receive HDLC Bit Suppress Register Register Address: 011h Bit # 7 6 Name BSE8 BSE7 Default 0 0 Bit 7: Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Register Address: 012h Bit # 7 6 Name — — Default 0 0 Bits Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a 5-bit channel ...
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Register Name: T1RCR2 (T1 Mode) Register Description: Receive Control Register 2 Register Address: 014h Bit # 7 6 Name — — Default 0 0 Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section 0 = SLC-96 synchronizer is disabled 1 ...
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Register Name: E1RSAIMR (E1 Mode Only) Register Description: Receive Sa-Bit Interrupt Mask Register Register Address: 014h Bit # 7 6 Name — — Default 0 0 Bit 4: Sa4 Change Detect Interrupt Mask (RSa4IM). This bit will enable the change ...
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Register Name: T1RBOCC (T1 Mode Only) Register Description: Receive BOC Control Register Register Address: 015h Bit # 7 6 Name RBR — Default 0 0 Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a ...
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Register Name: T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Register Description: Receive-Signaling All-Ones Insertion Registers Register Address: 038h, 039h, 03Ah Bit # (MSB Name CH8 CH7 CH16 CH15 CH24 CH23 Default 0 0 Setting any of ...
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Register Name: RS1 to RS16 Register Description: Receive-Signaling Registers Register Address: 040h to 04Fh T1 Mode: (MSB) CH1-A CH1-B CH1-C CH2-A CH2-B CH2-C CH3-A CH3-B CH3-C CH4-A CH4-B CH4-C CH5-A CH5-B CH5-C CH6-A CH6-B CH6-C CH7-A CH7-B ...
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Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 050h Bit # 7 6 Name LCVC15 LCVC14 Default 0 0 Bits Line Code Violation Counter Bits (LCVC[15:8]). LCVC15 is the ...
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Register Name: FOSCR1 Register Description: Frames Out of Sync Count Register 1 Register Address: 054h Bit # 7 6 Name FOS15 FOS14 Default 0 0 Bits Frames Out of Sync Counter Bits (FOS[15:8]). FOS15 ...
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Register Name: RDS0M Register Description: Receive DS0 Monitor Register Register Address: 060h Bit # 7 6 Name B1 B2 Default 0 0 Bits Receive DS0 Channel Bits (B[1:8]). Receive channel data that has been selected by the ...
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Register Name: T1RFDL (T1 Mode) Register Description: Receive FDL Register Register Address: 062h Bit # 7 6 Name RFDL7 RFDL6 Default 0 0 Note: This register has an alternate definition for E1 mode. See E1RRTS7. Bit 7: Receive FDL Bit ...
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Register Name: T1RBOC (T1 Mode) Register Description: Receive BOC Register Register Address: 063h Bit # 7 6 Name — — Default 0 0 Bit 5: BOC Bit 5 (RBOC5). Bit 4: BOC Bit 4 (RBOC4). Bit 3: BOC Bit 3 ...
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Register Name: T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Register Description: Receive SLC-96 Data Link Registers Register Address: 064h, 065h, 066h Bit # (MSB Name S=1 S4 Default 0 0 Note: These registers ...
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Register Name: E1RNAF (E1 Mode) Register Description: E1 Receive Non-Align Frame Register Register Address: 065h Bit # 7 6 Name Si 1 Default 0 0 Note: This register has an alternate definition for T1 mode. See T1RSLC2. Bit 7: International ...
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Register Name: E1RSiNAF (E1 Mode Only) Register Description: Receive Si Bits of the Non-Align Frame Register Register Address: 067h Bit # 7 6 Name SiF15 SiF13 Default 0 0 Bit 7: Si Bit of Frame 15 (SiF15). Bit 6: Si ...
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Register Name: E1RSa4 (E1 Mode Only) Register Description: Receive Sa4 Bits Register Register Address: 069h Bit # 7 6 Name RSa4F15 RSa4F13 Default 0 0 Bit 7: Sa4 Bit of Frame 15 (RSa4F15). Bit 6: Sa4 Bit of Frame 13 ...
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Register Name: E1RSa6 (E1 Mode Only) Register Description: Receive Sa6 Bits Register Register Address: 06Bh Bit # 7 6 Name RSa6F15 RSa6F13 Default 0 0 Bit 7: Sa6 Bit of Frame 15 (RSa6F15). Bit 6: Sa6 Bit of Frame 13 ...
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Register Name: E1RSa8 (E1 Mode Only) Register Description: Receive Sa8 Bits Register Register Address: 06Dh Bit # 7 6 Name RSa8F15 RSa8F13 Default 0 0 Bit 7: Sa8 Bit of Frame 15 (RSa8F15). Bit 6: Sa8 Bit of Frame 13 ...
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Register Name: Sa6CODE Register Description: Received Sa6 Codeword Register Register Address: 06Fh Bit # 7 6 Name — — Default 0 0 This register reports the received Sa6 codeword per ETS 300 233. The bits are monitored on a submultiframe ...
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Register Name: RCR1 (T1 Mode) Register Description: Receive Control Register 1 Register Address: 081h Bit # 7 6 Name SYNCT RB8ZS Default 0 0 Note: This register has an alternate definition for E1 mode. See RCR1. Bit 7: Sync Time ...
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Register Name: RCR1 (E1 Mode) Register Description: Receive Control Register 1 Register Address: 081h Bit # 7 6 Name — RHDB3 Default 0 0 Note: This register has an alternate definition for T1 mode. See Bit 6: Receive HDB3 Enable ...
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Register Name: T1RIBCC (T1 Mode) Register Description: Receive In-Band Code Control Register Register Address: 082h Bit # 7 6 Name — — Default 0 0 Note: This register has an alternate definition for E1 mode. See E1RCR2. Bits 5 to ...
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Register Name: E1RCR2 (E1 Mode) Register Description: Receive Control Register 2 Register Address: 082h Bit # 7 6 Name RSa8S RSa7S Default 0 0 Note: This register has an alternate definition for T1 mode. See T1RIBCC. Bit 7: Sa8 Bit ...
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Register Name: RCR3 Register Description: Receive Control Register 3 Register Address: 083h Bit # 7 6 Name — — Default 0 0 Bit 5: RSER Control (RSERC allow RSER to output data as received under all conditions (normal ...
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Register Name: RIOCR Register Description: Receive I/O Configuration Register Register Address: 084h Bit # 7 6 Name RCLKINV RSYNCINV RCLKINV RSYNCINV Default 0 0 Bit 7: RCLK Invert (RCLKINV inversion 1 = invert RCLK as input Bit ...
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Register Name: RESCR Register Description: Receive Elastic Store Control Register Register Address: 085h Bit # 7 6 Name RDATFMT RGCLKEN Default 0 0 Bit 7: Receive Channel Data Format (RDATFMT 64kbps (data contained in all 8 bits) 1 ...
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Register Name: ERCNT Register Description: Error-Counter Configuration Register Register Address: 086h Bit # 7 6 Name 1SECS MCUS 1SECS MCUS Default 0 0 Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between multiple ...
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Register Name: RHFC Register Description: Receive HDLC FIFO Control Register Register Address: 087h Bit # 7 6 Name — — Default 0 0 Bits 1 and 0: Receive FIFO High Watermark Select (RFHWM[1:0]). RFHWM1 RFHWM0 ...
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Register Name: RIBOC Register Description: Receive Interleave Bus Operation Control Register Register Address: 088h Bit # 7 6 Name — IBS1 Default 0 0 Bits 6 and 5: IBO Bus Size Bits (IBS[1:0]). Indicates how many devices on the bus. ...
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Register Name: T1RSCC (T1 Mode Only) Register Description: In-Band Receive Spare Control Register Register Address: 089h Bit # 7 6 Name — — Default 0 0 Bits Receive Spare Code Length Definition Bits (RSC[2:0]). RSC2 RSC1 RSC0 ...
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Register Name: RBPBS Register Description: Receive BERT Port Bit Suppress Register Register Address: 08Bh Bit # 7 6 Name BPBSE8 BPBSE7 Default 0 0 Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to ...
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Register Name: RLS1 Register Description: Receive Latched Status Register 1 Register Address: 090h Bit # 7 6 Name RRAIC RAISC Default 0 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Remote Alarm ...
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Register Name: RLS2 (T1 Mode) Register Description: Receive Latched Status Register 2 Register Address: 091h Bit # 7 6 Name RPDV — Default 0 0 Note: All bits in these register are latched. This register does not create interrupts. See ...
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Register Name: RLS2 (E1 Mode) Register Description: Receive Latched Status Register 2 Register Address: 091h Bit # 7 6 Name — CRCRC Default 0 0 Note: All bits in this register are latched. Bits can cause interrupts. ...
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Register Name: RLS3 (T1 Mode) Register Description: Receive Latched Status Register 3 Register Address: 092h Bit # 7 6 Name LORCC LSPC Default 0 0 Note: All bits in this register are latched and can create interrupts. See Bit 7: ...
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Register Name: RLS3 (E1 Mode) Register Description: Receive Latched Status Register 3 Register Address: 092h Bit # 7 6 Name LORCC — Default 0 0 Note: All bits in this register are latched and can create interrupts. See Bit 7: ...
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Register Name: RLS4 Register Description: Receive Latched Status Register 4 Register Address: 093h Bit # 7 6 Name RESF RESEM Default 0 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Elastic Store ...
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Register Name: RLS5 Register Description: Receive Latched Status Register 5 (HDLC) Register Address: 094h Bit # 7 6 Name — — Default 0 0 Note: All bits in this register are latched and can cause interrupts. Bit 5: Receive FIFO ...
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Register Name: RLS7 (T1 Mode) Register Description: Receive Latched Status Register 7 Register Address: 096h Bit # 7 6 Name — — Default 0 0 Note: All bits in this register are latched and can create interrupts. See Bit 5: ...
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Register Name: RSS1, RSS2, RSS3, RSS4 Register Description: Receive-Signaling Status Registers Register Address: 098h, 099h, 09Ah, 09Bh Bit # (MSB Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 Note: Status bits ...
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Register Name: T1RSCD1 (T1 Mode Only) Register Description: Receive Spare Code Definition Register 1 Register Address: 09Ch Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Spare ...
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Register Name: RIIR Register Description: Receive Interrupt Information Register Register Address: 09Fh Bit # 7 6 Name — RLS7 Default 0 0 *RLS6 is reserved for future use. **Currently, RLS2 does not create an interrupt, therefore this bit is not ...
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Register Name: RIM2 (E1 Mode Only) Register Description: Receive Interrupt Mask Register 2 Register Address: 0A1h Bit # 7 6 Name — — Default 0 0 Bit 3: Receive-Signaling All-Ones Event (RSA1 interrupt masked 1 = interrupt enabled ...
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Register Name: RIM3 (T1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Address: 0A2h Bit # 7 6 Name LORCC LSPC Default 0 0 Note: For E1 mode, see RIM3. Bit 7: Loss of Receive Clock Condition Clear (LORCC). ...
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Register Name: RIM3 (E1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Address: 0A2h Bit # 7 6 Name LORCC — Default 0 0 Note: For T1 mode, see RIM3. Bit 7: Loss of Receive Clock Clear (LORCC). 0 ...
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Register Name: RIM4 Register Description: Receive Interrupt Mask Register 4 Register Address: 0A3h Bit # 7 6 Name RESF RESEM Default 0 0 Bit 7: Receive Elastic Store Full Event (RESF interrupt masked 1 = interrupt enabled Bit ...
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Register Name: RIM5 Register Description: Receive Interrupt Mask Register 5 (HDLC) Register Address: 0A4h Bit # 7 6 Name — — Default 0 0 Bit 5: Receive FIFO Overrun (ROVR interrupt masked 1 = interrupt enabled Bit 4: ...
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Register Name: RIM7 (T1 Mode) Register Description: Receive Interrupt Mask Register 7 (BOC:FDL) Register Address: 0A6h Bit # 7 6 Name — — Default 0 0 Bit 5: Receive RAI-CI (RRAI-CI interrupt masked 1 = interrupt enabled Bit ...
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Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive-Signaling Change of State Enable Registers Register Address: 0A8h, 0A9h, 0AAh, 0ABh Bit # (MSB Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 ...
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Register Name: T1RUPCD1 (T1 Mode Only) Register Description: Receive Up Code Definition Register 1 Register Address: 0ACh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Up ...
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Register Name: T1RDNCD1 (T1 Mode Only) Register Description: Receive Down Code Definition Register 1 Register Address: 0AEh Bit # 7 6 Name C7 C6 Default 0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Down ...
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Register Name: RRTS1 Register Description: Receive Real-Time Status Register 1 Register Address: 0B0h Bit # 7 6 Name — — Default 0 0 Note: All bits in this register are real-time (not latched). Bit 3: Receive Remote Alarm Indication Condition ...
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Register Name: RRTS3 (T1 Mode) Register Description: Receive Real-Time Status Register 3 Register Address: 0B2h Bit # 7 6 Name — — Default 0 0 Note: All bits in this register are real-time (not latched). See Bit 3: Loss of ...
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Register Name: RRTS5 Register Description: Receive Real-Time Status Register 5 (HDLC) Register Address: 0B4h Bit # 7 6 Name — PS2 Default 0 0 Note: All bits in this register are real time. Bits Receive Packet Status ...
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Register Name: RHF Register Description: Receive HDLC FIFO Register Register Address: 0B6h Bit # 7 6 Name RHD7 RHD6 Default 0 0 Bit 7: Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. Bit 6: Receive ...
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Register Name: RCBR1, RCBR2, RCBR3, RCBR4 Register Description: Receive Channel Blocking Registers Register Address: 0C4h, 0C5h, 0C6h, 0C7h Bit # 7 6 Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 Bits 7 to ...
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Register Name: RGCCS1, RGCCS2, RGCCS3, RGCCS4 Register Description: Receive Gapped-Clock Channel Select Registers Register Address: 0CCh, 0CDh, 0CEh, 0CFh Bit # 7 6 Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 Bits 7 ...
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Register Name: RBPCS1, RBPCS2, RBPCS3, RBPCS4 Register Description: Receive BERT Port Channel Select Registers Register Address: 0D4h, 0D5h, 0D6h, 0D7h Bit # (MSB Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 ...
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Transmit Register Definitions Register Name: THC1 Register Description: Transmit HDLC Control Register 1 Register Address: 110h Bit # 7 6 Name NOFS TEOML Default 0 0 Bit 7: Number of Flags Select (NOFS send one flag between ...
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Register Name: THBSE Register Description: Transmit HDLC Bit Suppress Register Register Address: 111h Bit # 7 6 Name TBSE8 TBSE7 Default 0 0 Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this ...
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Register Name: E1TSACR (E1 Mode) Register Description: E1 Transmit Sa-Bit Control Register Register Address: 114h Bit # 7 6 Name SiAF SiNAF Default 0 0 Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF not ...
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Register Name: SSIE1, SSIE2, SSIE3, SSIE4 Register Description: Software-Signaling Insertion Enable Registers Register Address: 118h, 119h, 11Ah, 11Bh Bit # (MSB Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 Bits 7 ...
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Register Name: TS1 to TS16 Register Description: Transmit-Signaling Registers Register Address: 140h to 14Fh T1 Mode: Bit # (MSB Name CH1-A CH1-B CH2-A CH2-B CH3-A CH3-B CH4-A CH4-B CH5-A CH5-B CH6-A CH6-B CH7-A CH7-B CH8-A ...
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Register Name: TCICE1, TCICE2, TCICE3, TCICE4 Register Description: Transmit Channel Idle Code Enable Registers Register Address: 150h, 151h, 152h, 153h Bit # (MSB Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 ...
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Register Name: TFRID Register Description: Transmit Firmware Revision ID Register Register Address: 161h Bit # 7 6 Name FR7 FR6 Default 0 0 Bits Firmware Revision (FR[7:0]). This read-only register reports the transmitter firmware revision. Register Name: ...
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Register Name: T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode) Register Description: Transmit SLC-96 Data Link Registers Register Address: 164h, 165h, 166h Bit # (MSB Name S=1 S4 Default 0 0 Note: See E1TAF, ...
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Register Name: E1TSiAF (E1 Mode) Register Description: Transmit Si Bits of the Align Frame Register Register Address: 166h Bit # 7 6 Name TSiF14 TSiF12 Default 0 0 Bit 7: Si Bit of Frame 14 (TSiF14). Bit 6: Si Bit ...
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Register Name: E1TRA (E1 Mode Only) Register Description: Transmit Remote Alarm Register Register Address: 168h Bit # 7 6 Name TRAF15 TRAF13 Default 0 0 Bit 7: Remote Alarm Bit of Frame 15 (TRAF15). Bit 6: Remote Alarm Bit of ...
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Register Name: E1TSa5 (E1 Mode Only) Register Description: Transmit Sa5 Bits Register Register Address: 16Ah Bit # 7 6 Name TSa5F15 TSa5F13 Default 0 0 Bit 7: Sa5 Bit of Frame 15 (TSa5F15). Bit 6: Sa5 Bit of Frame 13 ...
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Register Name: E1TSa7 (E1 Mode Only) Register Description: Transmit Sa7 Bits Register Register Address: 16Ch Bit # 7 6 Name TSa7F15 TSa7F13 Default 0 0 Bit 7: Sa7 Bit of Frame 15 (TSa7F15). Bit 6: Sa7 Bit of Frame 13 ...
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Register Name: TMMR Register Description: Transmit Master Mode Register Register Address: 180h Bit # 7 6 Name FRM_EN INIT_DONE Default 0 0 Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 ...
Page 181
Register Name: TCR1 (T1 Mode) Register Description: Transmit Control Register 1 Register Address: 181h Bit # 7 6 Name TJC TFPT Default 0 0 Note: See TCR1 for E1 mode. Bit 7: Transmit Japanese CRC-6 Enable (TJC use ...
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Register Name: TCR1 (E1 Mode) Register Description: Transmit Control Register 1 Register Address: 181h Bit # 7 6 Name TTPT T16S Default 0 0 Note: See TCR1 for T1 mode. Bit 7: Transmit Time Slot 0 Pass Through (TTPT). 0 ...
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Register Name: TCR2 (T1 Mode) Register Description: Transmit Control Register 2 Register Address: 182h Bit # 7 6 Name TFDLS TSLC96 Default 0 0 Note: See TCR2 for E1 mode. Bit 7: TFDL Register Select (TFDLS source FDL ...
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Register Name: TCR2 (E1 Mode) Register Description: Transmit Control Register 2 Register Address: 182h Bit # 7 6 Name AEBE AAIS Default 0 0 Note: See TCR2 for T1 mode. Bit 7: Automatic E-Bit Enable (AEBE E-bits not ...
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Register Name: TCR3 Register Description: Transmit Control Register 3 Register Address: 183h Bit # 7 6 Name ODF ODM ODF ODM Default 0 0 Bit 7: Output Data Format (ODF bipolar data at TTIP and TRING 1 = ...
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Register Name: TIOCR Register Description: Transmit I/O Configuration Register Register Address: 184h Bit # 7 6 Name TCLKINV TSYNCINV TCLKINV TSYNCINV Default 0 0 Bit 7: TCLK Invert (TCLKINV inversion 1 = Invert Bit 6: TSYNC Invert ...
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Register Name: TESCR Register Description: Transmit Elastic Store Control Register Register Address: 185h Bit # 7 6 Name TDATFMT TGCLKEN Default 0 0 Note: Bits 7 and 6 are used for fractional backplane support. See Section 8.8.5. Bit 7: Transmit ...
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Register Name: TCR4 (T1 Mode Only) Register Description: Transmit Control Register 4 Register Address: 186h Bit # 7 6 Name — — Default 0 0 Bits 3: Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated ...
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Register Name: TIBOC Register Description: Transmit Interleave Bus Operation Control Register Register Address: 188h Bit # 7 6 Name — IBS1 Default 0 0 Bits 6 and 5: IBO Bus Size (IBS[1:0]). Indicates how many devices are on the bus. ...
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Register Name: TXPC Register Description: Transmit Expansion Port Control Register Register Address: 18Ah Bit # 7 6 Name — — Default 0 0 Bit 2: Transmit BERT Port Direction Control (TBPDIR Normal (line) operation. The transmit BERT port ...
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Register Name: TBPBS Register Description: Transmit BERT Port Bit Suppress Register Register Address: 18Bh Bit # 7 6 Name BPBSE8 BPBSE7 Default 0 0 Bit 7: Transmit Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to ...
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Register Name: TLS1 Register Description: Transmit Latched Status Register 1 Register Address: 190h Bit # 7 6 Name TESF TESEM TESF TESEM Default 0 0 Note: All bits in this register are latched and can cause interrupts. Bit 7: Transmit ...
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Register Name: TLS2 Register Description: Transmit Latched Status Register 2 (HDLC) Register Address: 191h Bit # 7 6 Name — — — — Default 0 0 Note: All bits in this register are latched and can create interrupts. Bit 4: ...
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Register Name: TIIR Register Description: Transmit Interrupt Information Register Register Address: 19Fh Bit # 7 6 Name — — Default 0 0 The Transmit Interrupt Information register provides an indication of which status registers are generating an interrupt. When an ...
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Register Name: TIM1 Register Description: Transmit Interrupt Mask Register 1 Register Address: 1A0h Bit # 7 6 Name TESF TESEM TESF TESEM Default 0 0 Bit 7: Transmit Elastic Store Full Event (TESF interrupt masked 1 = interrupt ...
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Register Name: TIM2 Register Description: Transmit Interrupt Mask Register 2 (HDLC) Register Address: 1A1h Bit # 7 6 Name — — — — Default 0 0 Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only interrupt masked ...
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Register Name: T1TCD1 (T1 Mode Only) Register Description: Transmit Code Definition Register 1 Register Address: 1ACh Bit # 7 6 Name C7 C6 Default 0 0 Bit 7: Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern. ...
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Register Name: TRTS2 Register Description: Transmit Real-Time Status Register 2 (HDLC) Register Address: 1B1h Bit # 7 6 Name — — Default 0 0 Note: All bits in this register are real time. Bit 3: Transmit FIFO Empty (TEMPTY). A ...
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Register Name: TDS0M Register Description: Transmit DS0 Monitor Register Register Address: 1BBh Bit # 7 6 Name B1 B2 Default 0 0 Bits Transmit DS0 Channel Bits (B[1:8]). Transmit channel data that has been selected by the ...
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Register Name: TCBR1, TCBR2, TCBR3, TCBR4 Register Description: Transmit Channel Blocking Registers Register Address: 1C4h, 1C5h, 1C6h, 1C7h Bit # (MSB) Name CH8 CH7 CH16 CH15 CH24 CH23 CH32 CH31 Default 0 0 Bits ...