PIC16F74-I/L Microchip Technology Inc., PIC16F74-I/L Datasheet - Page 19

• Manufacturer Part Number: PIC16F74-I/L
• Description: 44 PIN, 7 KB FLASH, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F74-I/L

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
 2002 Microchip Technology Inc.
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Bank 1
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
—
—
—
PR2
SSPADD
SSPSTAT
—
—
—
TXSTA
SPBRG
—
—
—
—
—
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter during branches ( CALL or GOTO ).
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
PSPIE
RBPU
CSRC
Bit 7
SMP
IRP
GIE
IBF
—
—
—
—
—
(3)
INTEDG
PEIE
ADIE
Bit 6
OBF
RP1
CKE
TX9
—
—
—
—
—
PORTA Data Direction Register
TMR0IE
TXEN
T0CS
IBOV
RCIE
2
Bit 5
RP0
D/A
C mode) Address Register
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
SYNC
T0SE
INTE
TXIE
Bit 4
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
—
—
—
S
PORTE Data Direction Bits
TMR0IF
CCP1IE
PCFG2
BRGH
Bit 2
R/W
PS2
—
—
Z
TMR2IE
PCFG1
TRMT
Bit 1
INTF
POR
PS1
DC
UA
—
PIC16F7X
TMR1IE
CCP2IE
PCFG0
TX9D
RBIF
Bit 0
BOR
PS0
BF
C
DS30325B-page 17
0000 0000
1111 1111 20, 44, 96
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
---0 0000
0000 000x
0000 0000
---- ---0
---- --qq
1111 1111
0000 0000
0000 0000
0000 -010
0000 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
on page
Details
27, 96
26, 96
19, 96
27, 96
32, 96
34, 96
35, 96
36, 96
38, 96
21, 96
23, 96
22, 96
24, 97
25, 97
52, 97
68, 97
60, 97
69, 97
71, 97
84, 97
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—
—
—
—
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