DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 205
![IC TXRX T1/E1/J1 8PORT 256-CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS26518GN+
Manufacturer Part Number
DS26518GN+
Description
IC TXRX T1/E1/J1 8PORT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Specifications of DS26518GN+
Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used.
Bit 6: Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used.
Bit 5: Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used.
Bit 4: Transmit Bit 5 Suppress (TBSE5). Set to one to stop this bit from being used.
Bit 3: Transmit Bit 4 Suppress (TBSE4). Set to one to stop this bit from being used.
Bit 2: Transmit Bit 3 Suppress (TBSE3). Set to one to stop this bit from being used.
Bit 1: Transmit Bit 2 Suppress (TBSE2). Set to one to stop this bit from being used.
Bit 0: Transmit Bit 1 Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to
be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be
cleared and set again for a subsequent abort to be sent.
Bit 6: Send BOC (SBOC) (T1 Mode Only). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the
register.
Bit 5: Transmit HDLC-64 Controller Enable (THCEN)
Bits 4 to 0: Transmit HDLC-64 Channel Select (THCS[4:0]). Determines which DSO channel will carry the
HDLC-64 message if enabled. Changes to this value are acknowledged only upon a transmit HDLC-64 controller
reset (THR at THC1.5).
0 = Transmit HDLC-64 controller is not enabled.
1 = Transmit HDLC-64 controller is enabled.
TBSE8
TABT
TABT
7
0
7
0
THBSE
Transmit HDLC-64 Bit Suppress
111h + (200h x (n - 1)) : where n = 1 to 8
THC2
Transmit HDLC-64 Control Register 2
113h + (200h x (n - 1)) : where n = 1 to 8
TBSE7
SBOC
—
6
0
6
0
THCEN
THCEN
TBSE6
5
0
5
0
THCS4
205 of 312
TBSE5
THCS4
0
0
4
4
THCS3
TBSE4
THCS3
3
0
3
0
THCS2
THCS2
TBSE3
2
0
2
0
THCS1
THCS1
TBSE2
1
0
1
0
T1TBOC
THCS0
THCS0
TBSE1
0
0
0
0
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