DS1100Z-50+ Dallas Semiconductor, DS1100Z-50+ Datasheet - Page 4
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DS1100Z-50+
Manufacturer Part Number
DS1100Z-50+
Description
Delay Line, 150 nS Max., 5-Tap Economy, 5 V Ops., -40 to 85 C, SOIC8
Manufacturer
Dallas Semiconductor
Datasheet
1.DS1100Z-50.pdf
(6 pages)
Specifications of DS1100Z-50+
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and 5V for both leading and
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if
4) Intermediate delay values are available on a custom basis. For further information, call
5) All voltages are referenced to ground.
6) Measured with outputs open.
7) See Test Conditions section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher I
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
Figure 3. TEST CIRCUIT
trailing edge.
temperature range, and a supply-voltage range of 4.75V to 5.25V.
TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
(972) 371-4348.
decoupling, layout).
4 of 6
CC
values.