PIC18F25K22-I/SO Microchip Technology Inc., PIC18F25K22-I/SO Datasheet - Page 93
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PIC18F25K22-I/SO
Manufacturer Part Number
PIC18F25K22-I/SO
Description
32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SOIC .300in TUBE
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F45K22-IP.pdf
(496 pages)
Specifications of PIC18F25K22-I/SO
A/d Inputs
17-Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
3-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number:
PIC18F25K22-I/SO
Manufacturer:
MICROCHIP
Quantity:
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Quantity:
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Part Number:
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Manufacturer:
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FIGURE 5-11:
2010 Microchip Technology Inc.
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
F60h
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
to
FFFh
Preliminary
FFFh
FFFh
F00h
F60h
FFFh
000h
060h
100h
F00h
F60h
000h
060h
100h
F00h
F60h
000h
060h
100h
Data Memory
Data Memory
Data Memory
Bank 15
Bank 15
Bank 15
Bank 14
Bank 14
Bank 14
Bank 0
through
Bank 0
through
Bank 0
through
Bank 1
Bank 1
Bank 1
SFRs
SFRs
SFRs
PIC18(L)F2X/4XK22
001001da
00000000
001001da
BSR
Access RAM
FSR2H
ffffffff
ffffffff
FSR2L
00h
60h
FFh
DS41412D-page 93
Valid range
for ‘f’
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