ENC28J60/SP Microchip Technology Inc., ENC28J60/SP Datasheet - Page 91

• Manufacturer Part Number: ENC28J60/SP
• Description: 28 PIN, 8 KB RAM, MAC&PHY, ETHERNET CONTROLLER
• Manufacturer: Microchip Technology Inc.
• Type: Controllerr

Specifications of ENC28J60/SP

• Package Type: 28-pin SSOP
• Voltage, Supply: 3.14-3.45 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

INDEX
B
Block Diagrams
Broadcast Filter ................................................................... 52
Built-in Self-Test Controller ................................................. 75
C
Checksum Calculations ...................................................... 72
CLKOUT Pin ......................................................................... 6
Control Register Map .......................................................... 12
Control Register Summary............................................ 13–14
Control Registers ................................................................ 12
Customer Change Notification Service ............................... 91
Customer Notification Service............................................. 91
Customer Support ............................................................... 91
D
DMA Controller ................................................................... 71
Duplex-Mode
E
Electrical Characteristics..................................................... 79
ENC28J60 Block Diagram .................................................... 3
EREVID Register ................................................................ 22
Errata .................................................................................... 2
Ethernet Buffer .................................................................... 17
Ethernet Module
© 2006 Microchip Technology Inc.
Crystal Oscillator Operation .......................................... 5
ENC28J60 Architecture ................................................ 3
Ethernet Buffer Organization ...................................... 18
External Clock Source .................................................. 5
External Connections.................................................... 7
I/O Level Shifting
Interrupt Logic ............................................................. 63
LEDB Polarity Configuration ......................................... 8
Memory Organization.................................................. 11
On-Chip Reset Circuit ................................................. 59
Typical Interface............................................................ 4
Address Fill Mode ....................................................... 76
Associated Registers .................................................. 77
EBSTCS registers....................................................... 76
EBSTSD Register ....................................................... 76
Pattern Shift Fill Mode................................................. 76
Random Data Fill Mode .............................................. 76
Use.............................................................................. 76
Access to Buffers ........................................................ 17
Associated Registers .................................................. 72
Checksum Calculations .............................................. 72
Copying Memory......................................................... 71
Configuration and Negotiation .................................... 53
Absolute Maximum Ratings ........................................ 79
AC Characteristics ...................................................... 81
CLKOUT Pin AC ......................................................... 81
DC Characteristics ...................................................... 80
Oscillator Timing ......................................................... 81
Requirements for External Magnetics......................... 81
Reset AC..................................................................... 81
SPI Interface AC ......................................................... 82
Organization (Diagram)............................................... 18
Transmitting and Receiving Data
3-State Buffers ...................................................... 8
AND Gate ............................................................. 8
Receive Packet Layout ....................................... 43
Transmit Packet Layout ...................................... 40
Preliminary
Ethernet Overview .............................................................. 31
External Connections (Diagram)........................................... 7
F
Filtering
Flow Control........................................................................ 55
Full-Duplex-Mode
H
Half-Duplex-Mode
Hash Table Filter ................................................................ 52
I
I/O Level Shifting .................................................................. 8
Initialization ......................................................................... 33
Interrupts ............................................................................ 63
L
LED Configuration ................................................................ 8
LEDB Polarity and Reset Configuration................................ 8
M
Magic Packet Filter ............................................................. 52
Magnetics and External Components................................... 7
Memory Organization ......................................................... 11
Multicast Filter..................................................................... 52
O
Oscillator............................................................................... 5
P
Packaging Information ........................................................ 83
Using AND Logic ........................................................ 50
Using OR Logic .......................................................... 49
Associated Registers.................................................. 57
Full-Duplex Mode ....................................................... 55
Half-Duplex Mode....................................................... 55
Sample Full-Duplex Network (Diagram) ..................... 55
Operation.................................................................... 53
Operation.................................................................... 53
Using 3-State Buffers ................................................... 8
Using AND Gates ......................................................... 8
MAC Settings.............................................................. 34
PHY Settings .............................................................. 37
Receive Buffer ............................................................ 33
Receive Filters............................................................ 33
Transmit Buffer ........................................................... 33
Waiting for OST .......................................................... 33
DMA Flag (DMAIF) ..................................................... 69
INT Enable (INTIE) ..................................................... 64
Link Change Flag (LINKIF)......................................... 69
Receive Error Flag (RXERIF) ..................................... 68
Receive Packet Pending Flag (PKTIF) ....................... 69
Transmit Error Flag (TXERIF) .................................... 68
Transmit Interrupt Flag (TXIF) .................................... 68
CLKOUT Transition ...................................................... 6
Crystal Oscillator .......................................................... 5
External Clock Source .................................................. 5
Start-up Timer............................................................... 5
Details......................................................................... 84
Marking....................................................................... 83
ENC28J60
DS39662B-page 89