PIC16LF1826-I/ML Microchip Technology Inc., PIC16LF1826-I/ML Datasheet - Page 329
PIC16LF1826-I/ML
Manufacturer Part Number
PIC16LF1826-I/ML
Description
3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16LF1826-I/ML
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin QFN
Programmable Memory
3.5K Bytes
Ram Size
256 Bytes
Speed
32 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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29.2
ADDFSR
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Description:
2011 Microchip Technology Inc.
Instruction Descriptions
Add W and f
[ label ] ADDWF
0 f 127
d 0,1
(W) + (f) (destination)
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADD W and CARRY bit to f
[ label ] ADDWFC
0 f 127
d [0,1]
(W) + (f) + (C) dest
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
[ label ] ADDFSR FSRn, k
n [ 0, 1]
FSR(n) + k FSR(n)
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
[ label ] ADDLW
0 k 255
(W) + k (W)
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
Add Literal to FSRn
-32 k 31
None
The signed 6-bit literal ‘k’ is added to
Add literal and W
C, DC, Z
f,d
k
f {,d}
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
ASRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
PIC16(L)F1826/27
AND W with f
[ label ] ANDWF
0 f 127
d 0,1
(W) .AND. (f) (destination)
Z
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
AND literal with W
[ label ] ANDLW
0 k 255
(W) .AND. (k) (W)
Z
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
Arithmetic Right Shift
[ label ] ASRF
0 f 127
d [0,1]
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
register f
f {,d}
DS41391D-page 329
f,d
k
C
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